D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 512

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
Bit 3: AIE
0
1
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register
(only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to
0 when 0 is written, but holds its previous value when 1 is written.
Bit 0: AF
0
1
Note: * Contents do not change when 1 is written to AF.
14.2.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit readable/writable register for periodic interrupt
control, 30-second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is
initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a
manual reset. It is not initialized, and retains its contents, in standby mode.
Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation with the period designated
by the PES bits. When set to 1, PEF generates periodic interrupts.
Bit 7: PEF
0
1
Rev. 5.0, 09/03, page 464 of 806
Initial value:
R/W:
Bit:
Description
An alarm interrupt is not generated when the AF flag is set to 1
An alarm interrupt is generated when the AF flag is set to 1
Description
Clock/calendar and alarm register have not matched since last reset to 0
Clearing condition: When 0 is written to AF
Setting condition: Clock/calendar and alarm register have matched (only
registers with ENB set) *
Description
Interrupts not generated with the period designated by the PES bits
Clearing condition: When 0 is written to PEF
Interrupts generated with the period designated by the PES bits
Setting condition: When 1 is written to PEF
PEF
R/W
7
0
PES2
R/W
6
0
PES1
R/W
5
0
PES0
R/W
4
0
RTCEN
R/W
3
1
R/W
ADJ
2
0
RESET
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
START
R/W
0
1