D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 495
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D6417729RHF200BV
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EVERLIGHT
Quantity:
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Part Number:
D6417729RHF200BV
Manufacturer:
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Input Capture Function: Channel 2 has an input capture function (figure 13.7). When using the
input capture function, set the TCLK pin to input mode with the TCOE bit in the timer output
control register (TOCR) and set the timer operation clock to internal clock or on-chip RTC clock
with the TPCS2–TPCS0 bits in the timer control register (TCR2). Also, designate use of the input
capture function and whether to generate interrupts on input capture with the IPCE1–IPCE0 bits in
TCR2, and designate the use of either the rising or falling edge of the TCLK pin to set the timer
counter (TCNT2) value into the input capture register (TCPR2) with the CKEG1–CKEG0 bits in
TCR2.
The input capture function cannot be used in standby mode.
clock input
input clock
RTC output
TCNT input
External Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select the external clock
(TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection
edge. Rising, falling, or both edges may be selected. The pulse width of the external clock
must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module
clock cycles for both edges. A shorter pulse width will result in accurate operation. Figure 13.5
shows the timing for both-edge detection.
On-Chip RTC Clock Operation: Set the TPSC2–TPSC0 bits in TCR to select the on-chip RTC
clock as the timer clock. Figure 13.6 shows the timing.
Figure 13.5 Count Timing when Operating on External Clock (Both Edges Detected)
External
TCNT
TCNT
TCNT
clock
clock
pin
Pφ
Figure 13.6 Count Timing when Operating on On-Chip RTC Clock
N + 1
N + 1
N
N
Rev. 5.0, 09/03, page 447 of 806
N − 1
N − 1
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