D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 584

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.2
This section describes the registers added for the smart card interface and the bits whose functions
are changed.
16.2.1
The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart
card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby
mode.
Bits 7 to 4 and 1—Reserved: These bits are always read as 0. The write value should always be
0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
0
1
Bit 2—Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the
data. This function is used in combination with bit 3 for transmitting and receiving with an inverse
convention card. SINV does not affect the logic level of the parity bit. See section 16.3.4, Register
Settings, for information on how parity is set.
Bit 2: SINV
0
1
Rev. 5.0, 09/03, page 536 of 806
Initial value:
Register Descriptions
Smart Card Mode Register (SCSCMR)
R/W:
Bit:
Description
Contents of SCTDR are transferred LSB-first, and receive data is stored in
SCRDR LSB-first
Contents of SCTDR are transferred MSB-first, and receive data is stored in
SCRDR MSB-first
Description
Contents of SCTDR are transferred unchanged, and receive data is stored
in SCRDR unchanged
Contents of SCTDR are inverted before transfer, and receive data is
inverted before storage in SCRDR
—
—
R
7
—
—
R
6
—
—
R
5
—
—
R
4
SDIR
R/W
3
0
SINV
R/W
2
0
—
—
R
1
(Initial value)
(Initial value)
SMIF
R/W
0
0