D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 473
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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CMCNT0 Count Timing
One of four clocks (P /4, P /8, P /16, P /64) obtained by dividing the P clock can be selected
with the CKS1 and CKS0 bits in CMCSR0. Figure 12.28 shows the timing.
CK
Internal clock
CMCNT0 input
clock
CMCNT0
N+1
N-1
N
Figure 12.28 Count Timing
12.4.4
Compare Match
Compare Match Flag Setting Timing
The CMF bit in the CMCSR0 register is set to 1 by the compare match signal generated when the
CMCOR0 register and the CMCNT0 counter match. The compare match signal is generated in the
final state of the match (timing at which the CMCNT0 counter matching count value is updated).
Consequently, after the CMCOR0 register and the CMCNT0 counter match, a compare match
signal will not be generated until a CMCNT0 counter input clock occurs. Figure 12.29 shows the
CMF bit setting timing.
Rev. 5.0, 09/03, page 425 of 806
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