D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 277

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.1.2
Table 9.2 lists the pins used for the power-down modes.
Table 9.2
Pin Name
Processing state 1
Processing state 0
Wakeup from
standby mode
Note: H: high level; L: low level
9.1.3
Table 9.3 shows the control register configuration for the power-down modes.
Table 9.3
Note: * Initialized by a power-on reset. This value is not initialized by a manual reset; the current
9.2
9.2.1
The standby control register (STBCR) is an 8-bit readable/writable register that sets the power-
down mode. STBCR is initialized to H'00 by a power-on reset. Always set bits 6–3 to 0 when
writing to the STBCR register.
Name
Standby control register
Standby control register 2
Initial value:
value is retained.
Pin Configuration
Register Configuration
Register Descriptions
Standby Control Register (STBCR)
Pin Configuration
Register Configuration
R/W:
Bit:
STBY
Symbol
STATUS1
STATUS0
WAKEUP
R/W
7
0
Abbreviation
STBCR
STBCR2
—
R
6
0
I/O
O
O
—
R
5
0
Description
Operating state of the processor.
HH: Reset, HL: Sleep mode, LH: Standby mode,
LL: Normal operation
Active-low assertion after accepting wakeup interrupt
in standby mode until returning to normal operation
with WDT overflow
R/W
R/W
R/W
STBXTL
R/W
4
0
Initial Value
H'00 *
H'00 *
—
R
3
0
Rev. 5.0, 09/03, page 229 of 806
Byte
Byte
Access Size
MSTP2
R/W
2
0
MSTP1
R/W
1
0
Address
H'FFFFFF82
H'FFFFFF88
MSTP0
R/W
0
0