D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 334

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.2.3
Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the
number of idle (wait) state cycles inserted for each area. For some memories, data bus drive may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. The SH7729R automatically
inserts the number of idle states set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling
timing.
Bit 15: WAITSEL
0
1
Note: * Operation is not guaranteed if WAIT is asserted while WAITSEL = 0.
Bits 14, 3, and 2 —Reserved: These bits are always read as 0. The write value should always be
0.
Rev. 5.0, 09/03, page 286 of 806
Initial value:
Initial value:
Wait State Control Register 1 (WCR1)
R/W:
R/W:
Bit:
Bit:
WAITSE
Description
Setting to 1 when using the WAIT signal *
Sampled WAIT signal at fall of CKIO
A3IW1
R/W
R/W
15
L
0
7
1
A3IW0
R/W
14
—
R
0
6
1
A6IW1
A2IW1
R/W
R/W
13
1
5
1
A6IW0
A2IW0
R/W
R/W
12
1
4
1
A5IW1
R/W
11
—
R
1
3
0
A5IW0
R/W
10
—
R
1
2
0
A4IW1
A0IW1
R/W
R/W
9
1
1
1
(Initial value)
A4IW0
A0IW0
R/W
R/W
8
1
0
1