D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 490

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.2.5
The timer counters are 32-bit readable/writable registers. The TMU has three timer counters, one
for each channel.
TCNT counts down upon input of a clock. The clock input is selected using the TPSC2–TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
Because the internal bus for the SH7729R on-chip peripheral modules is 16 bits wide, a time lag
can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To correct the discrepancy, a buffer register is connected to TCNT so that the upper and lower
halves are not read separately. The entire 32-bit data in TCNT can thus be read at once.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset, but is not initialized, and
retains its contents, in standby mode.
Rev. 5.0, 09/03, page 442 of 806
Initial value:
Initial value:
Initial value:
Initial value:
Timer Counters (TCNT)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
R/W
31
23
15
1
1
1
7
1
R/W
R/W
R/W
R/W
30
22
14
1
1
1
6
1
R/W
R/W
R/W
R/W
29
21
13
1
1
1
5
1
R/W
R/W
R/W
R/W
28
20
12
1
1
1
4
1
R/W
R/W
R/W
R/W
27
19
11
1
1
1
3
1
H'FFFFFFFF), the underflow
R/W
R/W
R/W
R/W
26
18
10
1
1
1
2
1
R/W
R/W
R/W
R/W
25
17
1
1
9
1
1
1
R/W
R/W
R/W
R/W
24
16
1
1
8
1
0
1