D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 175

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Pipeline Sequence:
Instruction n
Instruction n + 1
Instruction n + 2
Detection Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and general illegal instruction exception (instruction n + 2) = simultaneous detection
Handling Order:
TLB miss (instruction n)
Re-execution of instruction n
TLB miss (instruction n + 1)
Re-execution of instruction n + 1
RIE (instruction n + 2)
All exceptions other than a reset are detected in the pipeline ID stage, and accepted at instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
IF
ID
EX
MA
WB
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
Figure 4.2 Example of Acceptance Order of General Exceptions
IF
ID
IF
TLB miss (instruction access)
EX
ID
IF
MA
EX
Program Order:
TLB miss (data access)
ID
RIE (reserved instruction exception)
WB
MA
EX
1
2
3
WB
MA
WB
Rev. 5.0, 09/03, page 127 of 806