D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 451
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
D6417729RHF200BV
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EVERLIGHT
Quantity:
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Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR0–CHCR3.
Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (8-, 16-, or
32-bit unit) DMA transfer. When another transfer request occurs, the bus is obtained from the
other bus master and transfer is performed for one transfer unit. When that transfer ends, the
bus is passed to the other bus master. This is repeated until the transfer end conditions are
satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of the transfer request source,
transfer source, and transfer destination settings. Figure 12.14 shows an example of DMA
transfer timing in cycle-steal mode. Transfer conditions shown in the figure are:
Dual address mode
DREQ level detection
Bus cycle
DREQ
(External Memory Space (Ordinary Memory)
Figure 12.13 Example of DMA Transfer Timing in Single Address Mode
D31 to D0
A25 to A0
DACKn
CKIO
WEn
CPU
CSn
RD
Figure 12.14 Example of Transfer in Cycle-Steal Mode
CPU
source address
Transfer
CPU
DMAC DMAC
Read
+4
Write
Bus returned to CPU
CPU DMAC DMAC CPU
+8
External Device with DACK)
Read
Rev. 5.0, 09/03, page 403 of 806
+12
Write
CPU
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