D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 532

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15.2.7
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Note: * The only value that can be written is 0 to clear the flag.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
Bit 7: TDRE
0
1
Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF
0
1
Note: SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE
Rev. 5.0, 09/03, page 484 of 806
Initial value:
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive
data is lost.
Serial Status Register (SCSSR)
R/W:
Bit:
Description
SCTDR contains valid transmit data
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE or data is written in SCTDR.
SCTDR does not contain valid transmit data
TDRE is set to 1 when the chip is reset or enters standby mode, the TE bit in the
serial control register (SCSCR) is cleared to 0, or SCTDR contents are loaded
into SCTSR, so new data can be written in SCTDR.
Description
SCRDR does not contain valid receive data
RDRF is cleared to 0 when the chip is reset or enters standby mode, or software
reads RDRF after it has been set to 1, then writes 0 in RDRF.
SCRDR contains valid receive data
RDRF is set to 1 when serial data is received normally and transferred from
SCRSR to SCRDR.
R/(W) *
TDRE
7
1
R/(W) *
RDRF
6
0
R/(W) *
ORER
5
0
R/(W) *
FER
4
0
R/(W) *
PER
3
0
TEND
R
2
1
MPB
R
1
0
(Initial value)
(Initial value)
MPBT
R/W
0
0