D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet
D6417729RHF200BV
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D6417729RHF200BV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7729R Group 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH SH7700 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7729R Group Hardware Manual REJ09B0091-0500O ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The SH7729R is a microprocessor that integrates peripheral functions necessary for system configuration with a 32-bit internal architecture SH2-DSP CPU as its core. The SH7729R's on-chip peripheral functions include a cache memory, internal X/Y memory, an interrupt controller, timers, three ...
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User's Manuals on the SH7729R: Manual Title SH7729R Hardware Manual SH-3, SH-3E, SH-3DSP Programming Manual Users manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger User's Manual Embedded Workshop User's Manual Rev. 5.0, ...
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List of Items Revised or Added for This Version Section Page 1.2 Block Diagram 7 Figure 1.1 Block Diagram 5.4 Memory-Mapped 151, Cache 152 5.4.1 Address Array Description ASERAM deleted from figure BRIDGE UDI INTC CPG/WDT External bus interface ASERAM ...
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Section Page 5.4.2 Data Array 152 Rev. 5.0, 09/03, page x of xlvi Description Description amended The address array is mapped to H'F1000000 to H'F1FFFFFF. To access an element of the data array, the 32-bit address field (for read/write access) ...
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Section Page 5.5.1 Invalidating a 154 Specific Entry 5.5.2 Invalidating a 155 Specific Address 5.5.3 Reading the Data of a Specific Entry 7.2.6 Interrupt 171 Exception Handling and Priority Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) 7.3.6 ...
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Section Page 9.3.1 Transition to 233 Sleep Mode 9.5.1 Transition to 237 Module Standby Function 10.2.1 CPG Block 250 Diagram Figure 10.1 Block Diagram of Clock Pulse Generator Rev. 5.0, 09/03, page xii of xlvi Description Description added In sleep ...
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Section Page 10.3 Clock Operating 256 Modes Table 10.4 Available Combinations of Clock Mode and FRQCR Values 10.5.3 Notes on 259 Changing the Frequency 10.8.2 Changing the 265 Frequency 11.1.1 Features 11.2.5 Individual 292 Memory Control Register (MCR) 293 Description ...
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Section Page 11.2.13 MCS0 Control 304 Register (MCSCR0) 11.3.4 Synchronous 334 DRAM Interface 11.3.7 Waits between 363 Access Cycles Figure 11.40 Waits between Access Cycles 11.3.10 MCS[0] to 366 MCS[7] Pin Control 12.6 Usage Notes 431, 432 14.4.3 Precautions 470 ...
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Section Page 17.4 SCIF Interrupts 594 Table 17.10 SCIF Interrupt Sources 17.5 Usage Notes 595 20.13.2 SC Port Data 654 Register (SCPDR) Description Description amended When the TDFE flag in the serial status register (SCSSR) is set ...
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Section Page 21.3 Bus Master 665 Interface Figure 21.2 A/D Data Register Access Operation (Reading H'AA40) 24.1 Absolute 701 Maximum Ratings Table 24.1 Absolute Maximum Ratings 24.2 DC 703, Characteristics 705 Table 24.2 DC Characteristics Rev. 5.0, 09/03, page xvi ...
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Section Page 24.3.6 Synchronous 733 DRAM Timing Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2) 24.3.8 Peripheral 751 Module Signal Timing Figure 24.52 I/O Port Timing A.2 Pin Specifications 767 Table ...
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Section Page A.3 Treatment of 768 Unused Pins A.4 Pin States in 770 to Access to Each 782 Address Space Table A.3 Pin States (Ordinary Memory/Little Endian) Table A.4 Pin States (Ordinary Memory/Big Endian) Table A.5 Pin States (Burst ROM/Little ...
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Section 1 Overview ............................................................................................................. 1.1 Features ............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description .................................................................................................................. 1.3.1 Pin Assignment .................................................................................................... 1.3.2 Pin Function ......................................................................................................... 10 Section 2 CPU ....................................................................................................................... 19 2.1 Registers ............................................................................................................................ 19 2.1.1 General Registers ................................................................................................. 23 2.1.2 Control ...
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Configuration of the TLB ..................................................................................... 99 3.3.2 TLB Indexing ....................................................................................................... 101 3.3.3 TLB Address Comparison.................................................................................... 102 3.3.4 Page Management Information ............................................................................ 104 3.4 MMU Functions ................................................................................................................ 105 3.4.1 MMU Hardware Management ............................................................................. 105 3.4.2 MMU Software Management............................................................................... 105 3.4.3 ...
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Cautions............................................................................................................................. 140 Section 5 Cache .................................................................................................................... 143 5.1 Overview ........................................................................................................................... 143 5.1.1 Features ................................................................................................................ 143 5.1.2 Cache Structure .................................................................................................... 143 5.1.3 Register Configuration ......................................................................................... 145 5.2 Register Descriptions......................................................................................................... 145 5.2.1 Cache Control Register (CCR) ............................................................................. 145 5.2.2 Cache Control ...
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Interrupt Exception Handling and Priority ........................................................... 169 7.3 INTC Registers.................................................................................................................. 175 7.3.1 Interrupt Priority Registers (IPRA–IPRE) ................................................ 175 7.3.2 Interrupt Control Register 0 (ICR0) ..................................................................... 176 7.3.3 Interrupt Control Register 1 (ICR1) ..................................................................... 177 7.3.4 Interrupt ...
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Examples of Use................................................................................................... 220 8.3.9 Notes .................................................................................................................... 225 Section 9 Power-Down Modes 9.1 Overview ........................................................................................................................... 227 9.1.1 Power-Down Modes............................................................................................. 227 9.1.2 Pin Configuration ................................................................................................. 229 9.1.3 Register Configuration ......................................................................................... 229 9.2 Register Descriptions......................................................................................................... 229 9.2.1 Standby Control Register (STBCR) ...
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Notes on Changing the Frequency........................................................................ 259 10.6 Overview of WDT............................................................................................................. 260 10.6.1 Block Diagram of WDT ....................................................................................... 260 10.6.2 Register Configuration ......................................................................................... 260 10.7 WDT Registers .................................................................................................................. 261 10.7.1 Watchdog Timer Counter (WTCNT) ................................................................... 261 10.7.2 Watchdog Timer Control/Status ...
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MCS7 Control Register (MCSCR7)..................................................................... 305 11.3 BSC Operation .................................................................................................................. 306 11.3.1 Endian/Access Size and Data Alignment ............................................................. 306 11.3.2 Description of Areas............................................................................................. 311 11.3.3 Basic Interface...................................................................................................... 314 11.3.4 Synchronous DRAM Interface ............................................................................. 321 11.3.5 Burst ROM Interface ............................................................................................ 347 ...
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Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address On)........................................................................................... 429 12.6 Usage Notes....................................................................................................................... 431 Section 13 Timer (TMU) 13.1 Overview ........................................................................................................................... 433 13.1.1 Features ................................................................................................................ 433 13.1.2 Block Diagram ..................................................................................................... 434 13.1.3 Pin Configuration ................................................................................................. ...
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Second Alarm Register (RSECAR)...................................................................... 459 14.2.10 Minute Alarm Register (RMINAR) ..................................................................... 460 14.2.11 Hour Alarm Register (RHRAR) ........................................................................... 460 14.2.12 Day of Week Alarm Register (RWKAR)............................................................. 461 14.2.13 Date Alarm Register (RDAYAR) ........................................................................ 462 14.2.14 Month Alarm Register (RMONAR)..................................................................... ...
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Section 16 Smart Card Interface 16.1 Overview ........................................................................................................................... 533 16.1.1 Features ................................................................................................................ 533 16.1.2 Block Diagram ..................................................................................................... 534 16.1.3 Pin Configuration ................................................................................................. 535 16.1.4 Smart Card Interface Registers............................................................................. 535 16.2 Register Descriptions......................................................................................................... 536 16.2.1 Smart Card Mode Register (SCSCMR)................................................................ 536 ...
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Section 18 IrDA .................................................................................................................... 599 18.1 Overview ........................................................................................................................... 599 18.1.1 Features ................................................................................................................ 599 18.1.2 Block Diagram ..................................................................................................... 600 18.1.3 Pin Configuration ................................................................................................. 603 18.1.4 Register Configuration ......................................................................................... 604 18.2 Register Description .......................................................................................................... 605 18.2.1 Serial Mode Register (SCSMR) ........................................................................... 605 ...
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Port D Data Register (PDDR) .............................................................................. 638 20.6 Port E................................................................................................................................. 639 20.6.1 Register Description ............................................................................................. 639 20.6.2 Port E Data Register (PEDR) ............................................................................... 640 20.7 Port F................................................................................................................................. 641 20.7.1 Register Description ............................................................................................. 641 20.7.2 Port F Data Register (PFDR)................................................................................ ...
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Interrupts ........................................................................................................................... 674 21.6 Definitions of A/D Conversion Accuracy ......................................................................... 674 21.7 Usage Notes....................................................................................................................... 675 21.7.1 Setting Analog Input Voltage ............................................................................... 675 21.7.2 Processing of Analog Input Pins .......................................................................... 675 21.7.3 Access Size and Read Data .................................................................................. 676 Section ...
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AC Characteristics............................................................................................................. 706 24.3.1 Clock Timing........................................................................................................ 707 24.3.2 Control Signal Timing.......................................................................................... 713 24.3.3 AC Bus Timing .................................................................................................... 716 24.3.4 Basic Timing ........................................................................................................ 718 24.3.5 Burst ROM Timing .............................................................................................. 721 24.3.6 Synchronous DRAM Timing ............................................................................... 724 24.3.7 PCMCIA Timing.................................................................................................. 742 ...
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Figures Figure 1.1 Block Diagram ..................................................................................................... Figure 1.2 Pin Assignment (FP-208C, FP-208E) .................................................................. Figure 1.3 Pin Assignment (BP-240A).................................................................................. Figure 2.1 Register Configuration in Each Processing Mode (1) .......................................... 21 Figure 2.2 Register Configuration in Each Processing Mode (2) .......................................... 22 ...
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Figure 5.5 Write-Back Buffer Configuration......................................................................... 150 Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access...................... 153 Figure 6.1 X/Y Memory Logical Address Mapping.............................................................. 159 Figure 6.2 X/Y Memory Physical Address Mapping ............................................................ 160 Figure 7.1 Block Diagram of INTC....................................................................................... ...
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Figure 11.16 Basic Timing for Synchronous DRAM Single Read............................................ 328 Figure 11.17 Basic Timing for Synchronous DRAM Burst Write ............................................ 330 Figure 11.18 Basic Timing for Synchronous DRAM Single Write........................................... 332 Figure 11.19 Burst Read Timing (No Precharge) ...................................................................... 335 ...
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Figure 12.10 Example of Transfer Timing in the Indirect Address Mode in Dual Address Mode .................................................................................................................... 400 Figure 12.11 Data Flow in Single Address Mode...................................................................... 401 Figure 12.12 Example of DMA Transfer Timing in Single Address Mode .............................. 402 Figure ...
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Figure 15.4 SCPT[0]/RxD0 Pin............................................................................................... 475 Figure 15.5 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) ......................................................... 499 Figure 15.6 Output Clock and Serial Data Timing (Asynchronous Mode) ............................. 501 Figure 15.7 Sample Flowchart ...
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Figure 17.8 Example of Operation Using Modem Control (CTS)........................................... 588 Figure 17.9 Sample Flowchart for Receiving Serial Data ....................................................... 590 Figure 17.10 Sample Flowchart for Receiving Serial Data (cont)............................................. 591 Figure 17.11 Example of SCIF Receive Operation (8-Bit Data, Parity, ...
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Figure 24.4 Power-on Oscillation Settling Time ..................................................................... 709 Figure 24.5 Oscillation Settling Time on Return from Standby (Return by Reset) ................. 709 Figure 24.6 Oscillation Settling Time on Return from Standby (Return by NMI) .................. 710 Oscillation Settling Time on ...
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Figure 24.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1) ............................................................................... 738 Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 739 Figure 24.38 Synchronous DRAM Self-Refresh ...
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Tables Table 1.1 SH7729R Features .................................................................................................. Table 1.2 Characteristics......................................................................................................... Table 1.3 SH7729R Pin Functions.......................................................................................... 10 Table 2.1 Initial Register Values ............................................................................................ 22 Table 2.2 Operation of SR Bits in Each SH-3 DSP Mode...................................................... 29 Table 2.3 Destination Register in DSP ...
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Table 4.4 Types of Reset ........................................................................................................ 133 Table 5.1 Cache Specifications............................................................................................... 143 Table 5.2 LRU and Way Replacement ................................................................................... 145 Table 5.3 Register Configuration............................................................................................ 145 Table 5.4 LRU and Way Replacement (when W2LOCK=1) ................................................. 147 Table 5.5 LRU and Way ...
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Table 11.14 Example of Correspondence between SH7729R and Synchronous DRAM Address Pins (AMX2–0 = 011 (32-Bit Bus Width)) .............................................. 325 Table 11.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0–7).............................. 367 Table 12.1 DMAC Pins ............................................................................................................ 372 Table 12.2 DMAC ...
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Table 16.3 Register Settings for Smart Card Interface ............................................................. 541 Table 16.4 Relationship CKS1 and CKS0..................................................................... 543 Table 16.5 Examples of Bit Rate B (Bits/s) for SCBRR Settings (n Table 16.6 Examples of SCBRR Settings for Bit ...
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Table 20.22 Port L Data Register (PLDR) Read/Write Operation ............................................. 652 Table 20.23 SC Port Register ..................................................................................................... 653 Table 20.24 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 655 Table 21.1 A/D Converter Pins................................................................................................. 659 Table 21.2 A/D ...
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Rev. 5.0, 09/03, page xlvi of xlvi ...
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Features The SH7729R is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH RISC engine architecture CPU with a digital signal processing (DSP) extension as its core, together with cache memory, an on-chip X/Y memory, and a memory ...
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Table 1.1 SH7729R Features Item Features CPU Original Renesas Technology SuperH architecture Compatible with SH-1, SH-2, and SH-3 series at object code level 32-bit internal data bus General-registers Sixteen 32-bit general registers (eight 32-bit shadow registers) Eight 32-bit control registers ...
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Item Features Clock pulse Clock mode: Input clock can be selected from external input (EXTAL or generator (CPG) CKIO) or crystal oscillator Three types of clocks generated: CPU clock: 1–24 times the input clock, maximum 200 MHz Bus clock: 1–4 ...
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Item Features User break Two break channels controller (UBC) Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Bus state Physical address space divided into six areas (area ...
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Item Features Serial communi- 16-byte FIFO for transmission/reception cation interface 2 DMA transfer capability (SCI2) Hardware flow control Direct memory Four channels access controller Burst mode and cycle-steal mode (DMAC) Data transfer size: 8-/16-/32-bit and 16-byte I/O port Twelve 8-bit ...
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Table 1.2 Characteristics Item Characteristics Power supply voltage Operating frequency Process Note: * 2.0 +0.15 V, –0.1 V when using IRL and IRLS interrupts. Rev. 5.0, 09/03, page 6 of 806 I/O: 3.3 0.3 V, Internal: 2.0 0.15 V (200 ...
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Block Diagram XYCNT XYMEM MMU TLB CCN CACHE UDI INTC CPG/WDT Legend: ADC: A/D converter AUD: Advanced user debugger BSC: Bus state controller CACHE: Cache memory CCN: Cache memory controller CMT: Compare match timer CPG/WDT: Clock pulse generator/watchdog timer ...
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Pin Description 1.3.1 Pin Assignment Figure 1.2 shows the pin arrangement of the SH7729R. STATUS0/PTJ[6] 157 STATUS1/PTJ[7] 158 TCLK/PTH[7] 159 IRQOUT 160 V Q 161 SS CKIO 162 V Q 163 CC TxD0/SCPT[0] 164 SCK0/SCPT[1] 165 TxD1/SCPT[2] 166 SCK1/SCPT[3] ...
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(Top View ...
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Pin Function Table 1.3 shows the pin functions. Table 1.3 SH7729R Pin Functions Pin No. FP-208C, FP-208E BP-240A Pin Name 1 D2 MD1 2 C2 MD2 Vcc-RTC * XTAL2 5 D3 EXTAL2 Vss-RTC * 6 ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name 24 J4 D22/PTA[ D21/PTA[ D20/PTA[ Vss — K4 Vss 28 K1 D19/PTA[ Vcc — L4 Vcc 30 L2 D18/PTA[ D17/PTA[ D16/PTA[0] ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name VssQ VccQ ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name 83 W11 VssQ 84 T12 A24 85 U12 VccQ 86 V12 A25 BS/PTK[4] 87 W12 RD 88 T13 WE0/DQMLL 89 U13 WE1/DQMLU/WE 90 V13 WE2/DQMUL/ICIORD/ 91 W13 PTK[6] WE3/DQMUU/ICIOWR/ 92 T14 PTK[7] 93 ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name RAS3L/PTJ[0] 106 U18 107 U19 PTJ[1] CASL/PTJ[2] 108 R18 109 T19 VssQ CASU/PTJ[3] 110 T17 111 R19 VccQ 112 U17 PTJ[4] 113 R17 PTJ[5] 114 R16 DACK0/PTD[5] 115 P19 DACK1/PTD[7] 116 P18 PTE[6] ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name 132 K17 Vss — K16 Vss 133 K19 AUDATA[1]/PTG[1] 134 J17 Vcc — J16 Vcc 135 J18 AUDATA[0]/PTG[0] TRST/PTF[7]/PINT[15] 136 J19 137 H16 TMS/PTF[6]/PINT[14] 138 H17 TDI/PTF[5]/PINT[13] 139 H18 TCK/PTF[4]/PINT[12] IRLS3/PTF[3]/ 140 H19 ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name 154 E18 Vcc — C19 Vcc 155 C18 XTAL 156 D18 EXTAL 157 B16 STATUS0/PTJ[6] 158 B17 STATUS1/PTJ[7] 159 B15 TCLK/PTH[7] IRQOUT 160 A16 161 C16 VssQ 162 A15 CKIO 163 C17 VccQ ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name MCS[6]/PTC[6]/PINT[6] 178 D11 MCS[5]/PTC[5]/PINT[5] 179 C11 MCS[4]/PTC[4]/PINT[4] 180 B10 181 C10 VssQ WAKEUP/PTD[3] 182 D10 183 A10 VccQ RESETOUT/PTD[2] 184 C9 MCS[3]/PTC[3]/PINT[3] 185 D9 MCS[2]/PTC[2]/PINT[2] 186 B9 MCS[1]/PTC[1]/PINT[1] 187 A9 MCS[0]/PTC[0]/PINT[0] 188 D8 ...
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Pin No. FP-208C, FP-208E BP-240A Pin Name 201 C5 AN[2]/PTL[2] 202 D4 AN[3]/PTL[3] 203 A5 AN[4]/PTL[4] 204 C4 AN[5]/PTL[5] 205 A4 AVcc 206 B5 AN[6]/DA[1]/PTL[6] 207 B3 AN[7]/DA[0]/PTL[7] 208 B4 AVss Notes: 1. Must be connected to the power supply ...
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Registers The SH7729R has the same registers as the SH-3. In addition, the SH7729R also supports the same DSP-related registers as in the SH2-DSP. The basic software-accessible registers are divided into four distinct groups: General registers Control registers System ...
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This section explains the usage of these registers in different modes. Figures 2.1 and 2.2 show the register configuration in each processing mode. Switching between user mode and privileged mode is carried out by means of the operation mode bit ...
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R0_BANK0 * 2 R1_BANK0 * 2 R2_BANK0 * 2 R3_BANK0 * 2 R4_BANK0 * 2 R5_BANK0 * 2 R6_BANK0 * 2 R7_BANK0 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH ...
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DSP mode register configuration (DSP = 1) Figure 2.2 Register Configuration in Each Processing Mode (2) Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type General registers Control registers System registers DSP ...
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General Registers There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. With SuperH microcomputer type instructions used as an index register. With a number ...
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On the other hand, registers R2–R9 are also used for DSP data address calculation when DSP extension is enabled (see figure 2.4). Other symbols that represent the purpose of the registers in DSP type instructions is shown ...
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The name Ix is the alias for R8. Other aliases are as follows. Ax0: .REG (R4) Ax1: .REG (R5) Ix: .REG (R8) Ay0: .REG (R6) Ay1: .REG (R7) Iy: .REG (R9) This is optional, if another alias is required for ...
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SR also has a 12-bit repeat counter, RC, which is used for efficient loop control. The repeat start register (RS) and repeat end register (RE) are also provided for loop control. They hold the start and end addresses of a ...
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0-0 DSP MD bit: Processing mode bit Privileged mode User mode RB bit: Register bank bit; used to define the general ...
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MOD ME(Modulo end address) Saved status register (SSR) Stores current SR value at time of exception and returns value to SR when returning to instruction stream from exception or interrupt handler. Saved program ...
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Details of the status register (SR) when STC/LDC instructions are used are shown below. 1. When the DSP is not operating, operation is the same as for the SH- privileged DSP mode, operation is the same as in ...
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System Registers The SH7729R has four system registers, MACL, MACH, PR, and PC (figure 2.6). 31 MACH MACL The DSR, A0, X0, X1, Y0, and Y1 registers are also treated as system registers. Therefore, instructions ...
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The third kind of operation is a single-data transfer instruction, “MOVS.W” or “MOVS.L”. These instructions access any memory location through the LDB (figure 2.8). All DSP registers connect to the LDB and can be the source or destination register of ...
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Table 2.4 Source Register in DSP Operations Registers Instructions A0, A1 DSP Fixed-point, PDMSB, PSHA Integer Logical, PSHL, PMULS Data MOVX/Y.W, MOVS.W transfer MOVS.L A0G, A1G Data MOVS.W transfer MOVS.L X0, X1 DSP Fixed-point, PDMSB, Y0, Y1 PSHA M0, M1 ...
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Table 2.5 DSR Register Bits Bits Name (Abbreviation) 31–8 Reserved bits 7 Signed Greater Than bit (GT) 6 Zero bit (Z) 5 Negative bit (N) 4 Overflow bit (V) 3–1 Condition Select bits (CS) Designate the mode for selecting the ...
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MOVS.W, MOVS.L 39 A0G A1G DSR 7 Figure 2.8 Connections of DSP Registers and Buses The DSP unit has one DSP status register (DSR). DSR holds the status of DSP data operation results (zero, negative, and so on) ...
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Data Formats 2.2.1 Register Data Format (Non-DSP Type) Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only a byte (8 bits word (16 bits sign-extended into a longword when ...
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DSP type fixed point With guard bits Without guard bits Multiplier input DSP type integer With guard bits Without guard bits Shift amount for arithmetic shift (PSHA) Shift amount for logical shift (PSHL) DSP type logical CPU type integer Longword ...
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Memory Data Formats Memory data formats are classified into byte, word, and longword. Byte data can be accessed from any address, but an address error will occur if word data starting from an address other than 2n or longword ...
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Table 2.6 Word Data Sign Extension SH7729R CPU MOV.W @(disp,PC),R1 ADD R1,R0 ........ .DATA.W H'1234 Note: Immediate data is referenced by @(disp,PC). Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a ...
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T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a conditional branch is performed according to whether the result is True or False. Table 2.8 T Bit SH7729R CPU Description ...
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Absolute Addresses: When data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a ...
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Instruction Formats 2.4.1 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions Addressing Instruction Mode Format ...
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Addressing Instruction Mode Format Register @(disp:4, indirect with Rn) displacement Indexed @(R0, Rn) Effective address is sum of register Rn and R0 register indirect GBR indirect @(disp:8, with GBR) displacement Rev. 5.0, 09/03, page 42 of 806 Effective Address Calculation ...
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Addressing Instruction Mode Format Indexed GBR @(R0, indirect GBR) PC-relative with @(disp:8, displacement PC) Effective Address Calculation Method Effective address is sum of register GBR and R0 contents. GBR + R0 Effective address is PC with 8-bit displacement disp added. ...
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Addressing Instruction Mode Format PC-relative disp:8 disp:12 Rn Immediate #imm:8 #imm:8 #imm:8 Rev. 5.0, 09/03, page 44 of 806 Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied ...
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DSP Data Addressing Two different memory accesses are made with DSP instructions. The two kinds of instructions are X and Y data transfer instructions (MOVX.W, MOVY.W) and single data transfer instructions (MOVS.W, MOVSL). The data addressing is different for ...
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Increment address register addressing: The Ax and Ay registers are address pointers. After a data transfer, they are each incremented by 2 (post-increment). There is an index register for each address pointer. The R8 register is the index register ...
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Non-update address register addressing: The As register is an address pointer not updated. 2. Addition index register addressing: The As register is an address pointer. After a data transfer, the value of the Is register is added ...
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X or the Y address register, only; it cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set simultaneously. The MOD register is provided to set the start and ...
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As a result of the above settings, the R4 register changes as follows. R4: H'A5007008 Inc. R4: H'A500700A Inc. R4: H'A500700C Inc. R4: H'A5007008 Place the data so that the upper 16 bits of the modulo start and end addresses ...
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Table 2.14 CPU Instruction Formats Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx m type 15 0 xxxx mmmm xxxx xxxx Rev. 5.0, 09/03, page 50 of 806 Source Destination ...
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Instruction Format nm type 15 0 xxxx xxxx nnnn mmmm md type 15 0 xxxx xxxx mmmm dddd nd4 type 15 0 xxxx xxxx dddd nnnn nmd type 15 0 xxxx nnnn mmmm dddd Note multiply-and-accumulate instructions, nnnn ...
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Instruction Format d type 15 0 xxxx xxxx dddd dddd d12 type 15 0 xxxx dddd dddd dddd nd8 type 15 0 xxxx nnnn dddd dddd i type 15 0 xxxx xxxx ...
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DSP Instruction Formats The SH7729R includes new instructions for digital signal processing. The new instructions are of the following two kinds. 1. Memory and DSP register double and single data transfer instructions (16-bit length) 2. Parallel processing instructions processed ...
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Double and Single Data Transfer Instructions: The format of double data transfer instructions is shown in table 2.15, and that of single data transfer instructions in table 2.16. Table 2.15 Double Data Transfer Instruction Formats Type Mnemonic X memory NOPX ...
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Table 2.16 Single Data Transfer Instruction Formats Type Mnemonic Single MOVS.W @-As,Ds data MOVS.W @As,Ds transfer MOVS.W @As+,Ds MOVS.W @As+Is,Ds MOVS.W Ds,@-As MOVS.W Ds,@As MOVS.W Ds,@As+ MOVS.W Ds,@As+Is MOVS.L @-As,Ds MOVS.L @As,Ds MOVS.L @As+,Ds MOVS.L @As+Is,Ds MOVS.L Ds,@-As MOVS.L Ds,@As ...
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Table 2.17 A-Field Parallel Data Transfer Instructions Rev. 5.0, 09/03, page 56 of 806 ...
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Table 2.18 B-Field ALU Operation Instructions and Multiply Instructions Rev. 5.0, 09/03, page 57 of 806 ...
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Rev. 5.0, 09/03, page 58 of 806 ...
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Instruction Set 2.5.1 CPU Instruction Set The SH-1/SH-2/SH-3 compatible instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.19. Tables 2.20 to 2.25 show the instruction notation, machine code, execution time, ...
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Kinds of Type Instruction Arithmetic 21 operation instructions Logic 6 operation instructions Shift 12 instructions Rev. 5.0, 09/03, page 60 of 806 Op Code Function MULS Signed multiplication (16 MULU Unsigned multiplication (16 NEG Sign inversion NEGC Sign inversion with ...
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Kinds of Type Instruction Branch 9 instructions System 15 control instructions Total Code Function BF Conditional branch, delayed conditional branch ( Conditional branch, delayed conditional branch ( BRA Unconditional branch BRAF Unconditional branch ...
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The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Instruction Instruction Code Indicated by mnemonic. Indicated in MSB LSB order. Explanation ...
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Data Transfer Instructions Table 2.20 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn (disp MOV.W @(disp,PC),Rn extension (disp MOV.L @(disp,PC),Rn Rm MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn Rm MOV.L Rm,@Rn (Rm) MOV.B @Rm,Rn (Rm) MOV.W @Rm,Rn (Rm) MOV.L ...
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Instruction Operation Rm MOV.W Rm,@(R0,Rn) Rm MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn extension (R0 + Rm) MOV.W @(R0,Rm),Rn extension (R0 + Rm) MOV.L @(R0,Rm),Rn R0,@(disp,GBR) R0 MOV.B R0,@(disp,GBR) R0 MOV.W R0,@(disp,GBR) R0 MOV.L @(disp,GBR),R0 (disp + GBR) MOV.B extension ...
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Arithmetic Operation Instructions Table 2.21 Arithmetic Operation Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry ADDV Rm,Rn Overflow If R0 imm, 1 CMP/EQ #imm,R0 ...
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Instruction Operation Rn – else 0 A byte sign- EXTS.B Rm,Rn extended A word sign- EXTS.W Rm,Rn extended A byte zero- EXTU.B Rm,Rn extended A ...
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Logic Operation Instructions Table 2.22 Logic Operation Instructions Instruction Operation Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & imm AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm NOT Rm, Rm, ...
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Shift Instructions Table 2.23 Shift Instructions Instruction Operation T Rn ROTL Rn LSB ROTR ROTCL ROTCR << Rm SHAD Rm,Rn Rn < >> Rm [MSB T Rn SHAL ...
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Branch Instructions Table 2.24 Branch Instructions Instruction Operation disp BF label nop (where label is disp + PC) Delayed branch BF/S label disp nop Delayed branch, ...
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System Control Instructions Table 2.25 System Control Instructions Instruction Operation 0 MACH, MACL CLRMAC 0 S CLRS 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm SSR LDC Rm,SSR Rm SPC LDC Rm,SPC ...
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Instruction Operation (Rm) LDC.L @Rm R5_BANK (Rm) LDC.L @Rm R6_BANK (Rm) LDC.L @Rm R7_BANK Rm MACH LDS Rm,MACH Rm MACL LDS Rm,MACL Rm PR LDS Rm,PR (Rm) LDS.L @Rm+,MACH (Rm) LDS.L ...
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Instruction Operation Rn–4 STC.L SR,@–Rn Rn–4 STC.L GBR,@–Rn Rn–4 STC.L VBR,@–Rn Rn–4 STC.L SSR,@–Rn Rn–4 STC.L SPC,@–Rn Rn–4 STC.L R0_BANK, @–Rn Rn–4 STC.L R1_BANK, @–Rn Rn–4 STC.L R2_BANK, @–Rn Rn–4 STC.L R3_BANK, @–Rn Rn–4 STC.L R4_BANK, @–Rn Rn–4 STC.L R5_BANK, ...
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DSP Extended-Function Instructions 2.6.1 Introduction The DSP extended-function instructions are classified into the following three groups: 1. Additional system control instructions for the CPU unit (section 2.6.2, Added CPU System Control Instructions) 2. DSP unit memory-register single and double ...
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Table 2.26 Added CPU System Control Instructions Instruction Instruction Code 10000010iiiiiiii imm SETRC #imm 0100nnnn00010100 Rn[11:0] SETRC Rn 10001100dddddddd (disp 2 + PC) LDRS @(disp,PC) 10001110dddddddd (disp 2 + PC) LDRE @(disp,PC) 0000nnnn01010010 MOD STC MOD,Rn 0000nnnn01100010 RS STC RS,Rn ...
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Instruction Instruction Code 0100nnnn01110111 (Rn) LDC.L @Rn+,RE 0100nnnn01101010 Rn LDS Rn,DSR 0100nnnn01111010 Rn LDS Rn,A0 0100nnnn10001010 Rn LDS Rn,X0 0100nnnn10011010 Rn LDS Rn,X1 0100nnnn10101010 Rn LDS Rn,Y0 0100nnnn10111010 Rn LDS Rn,Y1 0100nnnn01011110 Rn LDC Rn,MOD 0100nnnn01101110 Rn LDC Rn,RS 0100nnnn01111110 ...
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Table 2.27 Double Data Transfer Instructions Instruction X memory NOPX data transfer MOVX.W @Ax,Dx MOVX.W @Ax+,Dx MOVX.W @Ax+Ix,Dx 111100A*D*0*11** (Ax) MOVX.W Da,@Ax MOVX.W Da,@Ax+ MOVX.W Da,@Ax+Ix 111100A*D*1*11** MSW memory NOPY data transfer MOVY.W @Ay,Dy MOVY.W @Ay+,Dy MOVY.W ...
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Table 2.28 Single Data Transfer Instructions Instruction Instruction Code 111101AADDDD0000 As – 2 MOVS.W @-As,Ds 111101AADDDD0100 (As) MOVS.W @As,Ds 111101AADDDD1000 (As) MOVS.W @As+,Ds 111101AADDDD1100 (Asc) MOVS.W @As+Ix,Ds 111101AADDDD0001 As – 2 MOVS.W Ds,@-As* 111101AADDDD0101 MSW of Ds MOVS.W Ds,@As* 111101AADDDD1001 ...
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The correspondence between DSP data transfer operands and registers is shown in table 2.29. CPU core registers are used as a pointer address that indicates a memory address. Table 2.29 Correspondence between DSP Data Transfer Operands and Registers Register CPU ...
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DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into ...
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Table 2.31 Correspondence between DSP Instruction Operands and Registers ALU and BPU Operations Register Yes A1 Yes M0 Yes M1 Yes X0 Yes X1 Yes Y0 Yes Y1 Yes When writing parallel instructions, the B-field instruction is ...
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Table 2.32 DSP Operation Instructions Instruction Instruction Code PMULS Se,Sf,Dg 111110********** 0100eeff0000gg00 PADD Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0111eeffxxyygguu PSUB Sx,Sy,Du 111110********** PMULS Se,Sf,Dg 0110eeffxxyygguu PADD Sx,Sy,Dz 111110********** 10110001xxyyzzzz DCT PADD Sx,Sy,Dz 111110********** 10110010xxyyzzzz DCF PADD Sx,Sy,Dz 111110********** 10110011xxyyzzzz PSUB Sx,Sy,Dz ...
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Instruction Instruction Code DCF PSHA Sx,Sy,Dz 111110********** 10010011xxyyzzzz PSHL Sx,Sy,Dz 111110********** 10000001xxyyzzzz DCT PSHL Sx,Sy,Dz 111110********** 10000010xxyyzzzz DCF PSHL Sx,Sy,Dz 111110********** 10000011xxyyzzzz PCOPY Sx,Dz 111110********** 11011001xx00zzzz PCOPY Sy,Dz 111110********** 1111100100yyzzzz DCT PCOPY Sx,Dz 111110********** 11011010xx00zzzz DCT PCOPY Sy,Dz 111110********** 1111101000yyzzzz ...
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Instruction Instruction Code PDMSB Sx,Dz 111110********** 10011101xx00zzzz PDMSB Sy,Dz 111110********** 1011110100yyzzzz DCT PDMSB Sx,Dz 111110********** 10011110xx00zzzz DCT PDMSB Sy,Dz 111110********** 1011111000yyzzzz DCF PDMSB Sx,Dz 111110********** 10011111xx00zzzz DCF PDMSB Sy,Dz 111110********** 1011111100yyzzzz PINC Sx,Dz 111110********** 10011001xx00zzzz PINC Sy,Dz 111110********** 1011100100yyzzzz DCT ...
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Instruction Instruction Code PNEG Sy,Dz 111110********** 1110100100yyzzzz DCT PNEG Sx,Dz 111110********** 11001010xx00zzzz DCT PNEG Sy,Dz 111110********** 1110101000yyzzzz DCF PNEG Sx,Dz 111110********** 11001011xx00zzzz DCF PNEG Sy,Dz 111110********** 1110101100yyzzzz POR Sx,Sy,Dz 111110********** 10110101xxyyzzzz DCT POR Sx,Sy,Dz 111110********** 10110110xxyyzzzz DCF POR Sx,Sy,Dz 111110********** ...
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Instruction Instruction Code PDEC Sy,Dz 111110********** 1010100100yyzzzz DCT PDEC Sx,Dz 111110********** 10001010xx00zzzz DCT PDEC Sy,Dz 111110********** 1010101000yyzzzz DCF PDEC Sx,Dz 111110********** 10001011xx00zzzz DCF PDEC Sy,Dz 111110********** 1010101100yyzzzz PCLR Dz 111110********** 100011010000zzzz DCT PCLR Dz 111110********** 100011100000zzzz DCF PCLR Dz 111110********** ...
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Instruction Instruction Code DCT PSTS MACL,Dz 111110********** 110111100000zzzz DCF PSTS MACL,Dz 111110********** 110111110000zzzz PLDS Dz,MACH 111110********** 111011010000zzzz DCT PLDS Dz,MACH 111110********** 111011100000zzzz DCF PLDS Dz,MACH 111110********** 111011110000zzzz PLDS Dz,MACL 111110********** 111111010000zzzz DCT PLDS Dz,MACL 111110********** 111111100000zzzz DCF PLDS Dz,MACL 111110********** ...
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Table 2.33 DC Bit Update Definitions CS [2:0] Condition Mode Carry or borrow mode Negative value mode Zero value mode Overflow mode Signed greater-than mode ...
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Conditional Operations and Data Transfer: Some DSP instruction can be executed conditionally, as described earlier. The specified condition is valid only for the B field of the instruction, and is not valid for data transfer instructions for which a parallel ...
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Table 2.34 Examples of NOPX and NOPY Instruction Codes Instruction PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 NOPX PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 MOVX.W @R4+,X0 NOPY MOVS.W @R4+,X0 NOPX NOPX NOP Code ...
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Rev. 5.0, 09/03, page 90 of 806 ...
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Section 3 Memory Management Unit (MMU) 3.1 Overview 3.1.1 Features The SH7729R has an on-chip memory management unit (MMU) that implements address translation. The SH7729R features a resident translation look-aside buffer (TLB) that caches information for user-created address translation tables ...
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MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by ...
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Process 1 Physical memory Process 1 Process 1 Process 2 Process 3 Figure 3.1 MMU Functions Virtual memory Process 1 Physical memory (1) Virtual Process 1 memory Physical memory Process 2 Process 3 (3) Rev. 5.0, 09/03, page 93 of ...
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SH7729R MMU Virtual Address Space: The SH7729R uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. (a) Privileged Mode In privileged mode, there ...
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H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) H'A0000000 0.5-Gbyte fixed physical space, non-cacheable H'C0000000 0.5-Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5-Gbyte control space, non-cacheable H'FFFFFFFF Privileged mode Figure 3.2 Virtual Address Space Mapping Physical ...
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If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and ...
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Register Configuration Table 3.1 shows the configuration of the MMU control registers. Table 3.1 Register Configuration Name Page table entry register high PTEH Page table entry register low Translation table base register TLB exception address register MMU control register ...
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The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in the area. The MMU registers are shown in figure 3.3. ...
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TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the ...
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VPN (31−17) VPN (11−10) ASID Legend VPN: Virtual page number. Upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16−12 are ...
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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits and ASID bits PTEH are used as the index number. The index number ...
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Virtual address Index 0 VPN(31−17) VPN(11−10) 31 Address array 3.3.3 TLB Address Comparison A TLB address comparison is performed when an instruction is fetched from a program in external memory or data in external memory is referenced. ...
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The sharing information (SH) determines whether PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH when there is sharing (SH 1). When single virtual memory is supported (MMUCR.SV ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., ...
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MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the ...
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MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR ...
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MMUCR Index PTEH register VPN VPN Write VPN(31−17) VPN(11−10 Address array Figure 3.9 Operation of LDTLB Instruction 3.4.4 Avoiding Synonym Problems When a 1-kbyte ...
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Note: When multiple address information items use the same physical memory to provide for future expansion of the SuperH RISC engine family recommended that VPN[20:10] be made equal. Also, the same physical addresses should not be used with ...
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When using a 4-kbyte page Virtual address VPN Physical address 000 PPN When using a 1-kbyte page Virtual address 31 11 VPN Physical address PPN 000 Figure ...
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MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss exception occurs when the virtual address and the address array of the selected TLB ...
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If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue an LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue an RTE ...
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TLB Invalid Exception A TLB invalid exception occurs when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid ...
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Initial Page Write Exception An initial page write exception occurs in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is ...
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No VPNs match? TLB miss exception PR check 00/01 W R/W? TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.11 MMU Exception Generation Flowchart Rev. 5.0, 09/03, page 114 of 806 Start ...
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Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) MMU Exception in Instruction Fetch Mode TLB-related exception signals in an instruction fetch : Exception source stage IF = Instruction fetch ID = Instruction decode EX ...
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MMU Exception in Data Access Mode TLB-related exception signals in a data access Exception source stage : Stage cancellation for instruction that has begun execution IF = Instruction fetch ID = Instruction decode EX = Instruction ...
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MMU Exception in Repeat Loop When an MMU exception or CPU address error occurs immediately before or within a repeat loop, the PC of the instruction that generated the exception cannot be saved in SPC correctly and the repeat ...
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SR.RC=2) inst inst0 inst1 inst2 IF : instN-3 instN-2 instN-1 instN inst1 inst2 : instN-3 ...
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When writing, the write is performed to the entry selected with the index address and way. When reading, the VPN, V bit, and ASID of the entry selected with the index address and way in the format of the data ...
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TLB Address Array Access · Read access 31 Address field 31 Data field · Write access 31 Address field 31 Data field VPN (2) TLB Data Array Access · Read/write access 31 Address field 31 Data field ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 30 ; MMUCR.IX=0 ; VPN(31–17)=B'0001 0101 ...
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Rev. 5.0, 09/03, page 122 of 806 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Features Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception handling request due to abnormal termination of the ...
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PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception handling sequence consists of the following operations: 1. The contents of PC and SR ...
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Table 4.2 Exception Event Vectors Exception Current Type Instruction Exception Event Reset Aborted Power-on reset Manual reset UDI reset General Aborted CPU address error exception and retried (instruction access) events TLB miss (instruction access not in repeat loop) TLB miss ...
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Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest. 2. The user defines the break point traps break point before instruction execution and break point after ...
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Pipeline Sequence: Instruction Instruction TLB miss (instruction access) Instruction Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and general illegal instruction exception (instruction simultaneous ...
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Exception Codes Table 4.3 lists the exception codes written to EXPEVT register (for reset or general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to identify each specific exception event. Table 4.3 Exception Codes Exception Type ...
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Exception Type General interrupt requests (cont) 4.2.5 Exception Request Masks When the BL bit exceptions and interrupts are accepted general exception event occurs when the BL bit the CPU’s internal ...
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Register Descriptions There are four registers related to exception handling. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in privileged mode only. 1. The exception event register (EXPEVT) ...
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Exception Handling Operation 4.4.1 Reset The reset sequence is used to power up or restart the SH7729R from the initialization state. The RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset, ...
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General Exceptions When the SH7729R encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of PC and SR are saved to SPC and SSR, respectively. 2. The BL bit ...
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UDI Reset Conditions: UDI reset command input (see section 23.4.3, UDI Reset) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are ...
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TLB invalid exception Conditions: Comparison of TLB addresses shows address match but the TLB entry valid bit ( Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number ...
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TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR Privileged mode 00 Only read enabled 01 Read/write enabled 10 Only read enabled 11 Read/write enabled Operations: The virtual address (32 bits) ...
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Operations: The virtual address (32 bits) that caused the exception is set in TEA. PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is ...
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Operations: PC and SR of the instruction that generated the exception are saved to SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to ...
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Operations the instruction immediately after the instruction executed before the exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR ...
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PINT Pin Interrupts Conditions: The PINT pin is asserted, the interrupt mask bits in SR are lower than the PINT priority level, and the BL bit The interrupt is accepted at an instruction boundary. Operations: ...
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Cautions Return from exception handling Check the BL bit in SR with software. When SPC and SSR have been saved to external memory, set the BL bit before restoring them. Issue an RTE instruction, which ...
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When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This will be identified ...
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Rev. 5.0, 09/03, page 142 of 806 ...
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Overview 5.1.1 Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity 16 kbytes Structure Instructions/data mixed, 4-way set associative Locking Way 2 and way 3 are lockable Line size 16 bytes Number ...
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Address array (ways 0−3) Entry Tag address Entry Entry 255 22) bits Address Array: The V bit indicates whether the entry data is valid. When ...
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Table 5.2 LRU and Way Replacement LRU (5–0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 5.1.3 Register Configuration Table 5.3 shows details of ...
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Bits 5, 4: Always set to 0 when setting the register. CF: Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all cache entries to 0). Always ...
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W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit. When W2LOCK = 1 & W2LOAD = 1 & DSP = 1, the prefetched data will always be loaded into way 2. In all other conditions the prefetched data ...
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Table 5.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) LRU (5–0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 5.3 Cache Operation 5.3.1 ...
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Virtual address Entry selection Tag address MMU 1 255 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 ...
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Read Access Read Hit read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. LRU is updated. Read Miss: An external bus cycle starts and the entry is ...
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Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is accessed, the latest data may write-back mode cache, ...
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V bit specified in the data field are then written. Note that, when written to the V bit should always be written to the U bit of the same entry, too. (3) Address Array ...