D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 166

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.6
In order for TLB operations to be managed by software, TLB contents can be read or written to in
privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000–
H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000–H'F3FFFFFF.
The V bit in the address array can also be accessed from the data array. Only longword access is
possible for both the address array and the data array.
3.6.1
The address array is assigned to H'F2000000–H'F2FFFFFF. To access an address array, the
32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 3.15 (1)).
In the address field, specify VPN (16–12) as the index address for selecting the entry (bits 16–12),
the W bits for selecting the way (bits 9–8), and H'F2 to indicate address array access (bits 31–24).
The IX bit in MMUCR indicates whether the EX-OR of VPN (16–12) and ASID (4–0) in the
PTEH register is used as the index address.
Rev. 5.0, 09/03, page 118 of 806
(4) 4 or more instructions repeated (inst1, inst2, ..., instN, SR.RC=2)
inst-1
inst0
inst1
inst2
instN-3
instN-2
instN-1
instN
inst1
inst2
instN-3
instN-2
instN-1
instN
instN+1
:
:
Memory-Mapped TLB
Address Array
IF
ID
IF
EX MA WB
ID
IF
Figure 3.14 MMU Exception in Repeat Loop (cont)
: Exception source stage where SPC is not correct
EX MA WB
ID
IF
and repeat loop can not be restarted
EX MA WB
ID
EX MA WB
IF
ID
IF
:
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
EX MA WB
IF
ID
IF
:
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
IF
EX MA WB
ID
EX MA WB