D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 69
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
31
(a) User mode register
2. Bank register
3. Bank register
4. Bank register
configuration
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
and indexed GBR indirect addressing mode.
Figure 2.1 Register Configuration in Each Processing Mode (1)
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
MACH
MACL
GBR
R10
R12
R13
R14
R15
R11
SR
PR
PC
R8
R9
*
1
*
*
*
*
*
*
*
2
2
2
2
2
2
2
*
2
0
31
(b) Privileged mode register
configuration (RB = 1)
R0_BANK1
R0_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
SSR
GBR
VBR
SPC
R10
R12
R13
R14
R15
R11
SR
PR
PC
R8
R9
*
*
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
3
3
3
3
3
3
3
4
4
4
4
4
4
4
*
3
4
0
31
(c) Privileged mode register
configuration (RB = 0)
R0_BANK1
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
Rev. 5.0, 09/03, page 21 of 806
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*
*
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
4
4
4
4
4
4
4
3
3
3
3
3
3
3
*
3
4
0
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