D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 533
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
Bit 4—Framing Error (FER): Indicates that data reception aborted due to a framing error in
asynchronous mode.
Bit 5: ORER
0
1
Bit 4: FER
0
1
2. SCRDR continues to hold the data received before the overrun error, so subsequent
retains its previous value.
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In
synchronous mode, serial transmitting is also disabled.
Description
Receiving is in progress or has ended normally *
ORER is cleared to 0 when the chip is reset or enters standby mode, or when
software reads ORER after it has been set to 1, then writes 0 to ORER.
A receive overrun error occurred *
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
Description
Receiving is in progress or has ended normally
Clearing the RE bit to 0 in the serial control register does not affect the FER bit,
which retains its previous value.
FER is cleared to 0 when the chip is reset or enters standby mode, or when
software reads FER after it has been set to 1, then writes 0 to FER.
A receive framing error occurred
When the stop bit length is two bits, only the first bit is checked. The second stop
bit is not checked. When a framing error occurs, the SCI transfers the receive
data into SCRDR but does not set RDRF. Serial receiving cannot continue while
FER is set to 1. In synchronous mode, serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
2
1
Rev. 5.0, 09/03, page 485 of 806
(Initial value)
(Initial value)
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