D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 121

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.6
2.6.1
The DSP extended-function instructions are classified into the following three groups:
1. Additional system control instructions for the CPU unit (section 2.6.2, Added CPU System
2. DSP unit memory-register single and double data transfer (section 2.6.3, Single and Double
3. DSP unit parallel processing (section 2.6.4, DSP Operation Instruction Set)
2.6.2
The instructions in this class are treated as part of the CPU core functions, and therefore all the
added instructions have a 16-bit code length. All the additional instructions belong to the system
control instruction group. Table 2.26 summarizes the added system instructions.
Control registers—RS, RE, and MOD—have been added to the CPU core to support loop control
and modulo addressing functions, and LDC and STS instructions have been provided for these
registers.
The DSP engine’s DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as
STS and LDS instructions are supported for these registers. As digital signal processing operations
usually employ a multi-level nested-loop structure, DSP performance can be improved by means
of a zero-overhead loop control function. SETRC instructions are provided to set the repeat count
in the RC field in SR[27:16]. When an immediate operand type SETRC instruction is executed,
the 8-bit immediate operand data is set in SR[23:16], and 0 is set in the remaining bits, SR[27:24].
When a register operand type SETRC instruction is executed, Rn[11:0] is set in SR[27:16]. The
start address and end address of the repeat loop are set in the RS register and RE register. There
are two ways of setting the addresses: by using an LDC instruction, or by using the LDRS and
LDRE instructions.
Control Instructions)
Data Transfer for DSP Data Instructions)
DSP Extended-Function Instructions
Introduction
Added CPU System Control Instructions
Rev. 5.0, 09/03, page 73 of 806