D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 194

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.2.2
CCR2 register is used to enable or disable the cache locking mechanism in DSP mode (set by CPU
status register bit 12) only. Executing a prefetch instruction (PREF) in DSP mode will bring the
line of data pointed to by Rn into the cache, according to the setting of CCR2 [9:8] (W3LOAD,
W3LOCK) and [1:0] (W2LOAD, W2LOCK).
When CCR2[9:8]=11, in DSP mode PREF @Rn will bring the data into way 3. When
CCR2[9:8]=00, 01, or 10 in DSP mode, or any setting in non-DSP mode, PREF @Rn will place
the data into the way pointed to by LRU.
When CCR2[1:0]=11, in DSP mode PREF @Rn will bring the data into way 2. When
CCR2[1:0]=00, 01, or 10 in DSP mode, or any setting in non-DSP mode, PREF @Rn will place
the data into the way pointed to by LRU.
CCR2 must be set before the cache is enabled (CCR.CE = 1).
When a PREF instruction is issued and there is a cache hit, the operation is treated as NOP.
Figure 5.3 shows the configuration of the CCR2 register.
CCR2 is a write-only register; if read, an undefined value will be returned.
Rev. 5.0, 09/03, page 146 of 806
Bits 5, 4: Always set to 0 when setting the register.
CF:
CB:
WT:
CE:
31
Cache Control Register 2 (CCR2)
…
Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all
cache entries to 0). Always reads 0. Write-back to external memory is not performed when
the cache is flushed.
Cache write-back bit. Indicates the cache's operating mode for area P1.
1 = write-back mode, 0 = write-through mode.
Write-through bit. Indicates the cache's operating mode for areas P0, U0, and P3.
1 = write-through mode, 0 = write-back mode.
Cache enable bit. Indicates whether the cache function is used.
1 = cache used, 0 = cache not used.
…
…
Figure 5.2 CCR Register Configuration
…
…
…
…
…
6
0
5
0
4
CF
3
CB
2
WT
1
CE
0