D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 633

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Figure 17.6 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
1. SCIF status check and transmit data write:
2. Serial transmission continuation procedure:
3. Break output at the end of serial transmission:
In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the
number of transmit data bytes in SCFTDR indicated by the upper 8 bits of the FIFO data count
register (SCFDR).
Serial data transmission
Read serial status register (SCSSR) and check that the TDFE flag is set to 1, then write
transmit data to the transmit FIFO data register (SCFTDR), read 1 from the TDFE and TEND
flags, then clear these flags to 0.
The number of transmit data bytes that can be written is (16 - transmit trigger set number).
To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible,
then write data to SCFTDR, and then clear the TDFE flag to 0.
To output a break in serial transmission, set the port SC data register (SCPDR) and port SC
control register (SCPCR), then clear the TE bit to 0 in the serial control register (SCSCR). For
information on SCPDR and SCPCR, see section 17.2.8, Bit Rate Register (SCBRR).
Rev. 5.0, 09/03, page 585 of 806