D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 357

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 11.10 32-Bit External Device/Little-Endian Access and Data Alignment
Table 11.11 16-Bit External Device/Little-Endian Access and Data Alignment
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword
access
at 0
1st time
at 0
2nd time
at 2
D31–D24 D23–D16 D15–D8
—
—
—
Data
7–0
—
Data
15–8
Data
31–24
D31–
D24
—
—
—
—
—
—
—
—
—
—
Data
7–0
—
—
Data 7–0
Data
23–16
D23–
D16
—
—
—
—
—
—
—
—
Data Bus
Data Bus
—
Data
7–0
—
—
Data
15–8
—
Data
15–8
D15–D8
—
Data
7–0
—
Data
7–0
Data
15–8
Data
15–8
Data
15–8
Data
31–24
D7–D0
Data
7–0
—
Data
7–0
—
Data
7–0
Data
7–0
Data
7–0
Data
23–16
D7–D0
Data
7–0
—
—
—
Data
7–0
—
Data
7–0
W W W W E E E E 3 3 3 3 ,
DQMUU
W W W W E E E E 3 3 3 3 ,
DQMUU
Asserted
Asserted
Asserted
Rev. 5.0, 09/03, page 309 of 806
W W W W E E E E 2 2 2 2 ,
DQMUL
W W W W E E E E 2 2 2 2 ,
DQMUL
Asserted
Asserted
Asserted
Strobe Signals
Strobe Signals
W W W W E E E E 1 1 1 1 ,
DQMLU
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
W W W W E E E E 1 1 1 1 ,
DQMLU
Asserted
Asserted
Asserted
W W W W E E E E 0 0 0 0 ,
DQMLL
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
W W W W E E E E 0 0 0 0 ,
DQMLL
Asserted
Asserted
Asserted