D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 530

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is
ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
1
Rev. 5.0, 09/03, page 482 of 806
Description
Transmitter disabled
The transmit data register empty bit (TDRE) in the serial status register (SCSSR)
is fixed at 1.
Transmitter enabled
Serial transmission starts when the transmit data register empty (TDRE) bit in the
serial status register (SCSSR) is cleared to 0 after writing of transmit data into the
SCTDR. Select the transmit format in SCSMR before setting TE to 1.
Description
Receiver disabled
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER).
These flags retain their previous values.
Receiver enabled
Serial reception starts when a start bit is detected in asynchronous mode, or
synchronous clock input is detected in synchronous mode. Select the receive
format in SCSMR before setting RE to 1.
Description
Multiprocessor interrupts are disabled (normal receive operation)
MPE is cleared to 0 when MPIE is cleared to 0, or the multiprocessor bit (MPB) is
set to 1 in receive data.
Multiprocessor interrupts are enabled
Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI),
and setting of the RDRF, FER, and ORER status flags in the serial status register
(SCSSR) are disabled until data with a multiprocessor bit of 1 is received.
The SCI does not transfer receive data from SCRSR to SCRDR, does not detect
receive errors, and does not set the RDRF, FER, and ORER flags in the serial
status register (SCSSR). When it receives data that includes MPB
SCSSR’s MPB flag is set to 1, and the SCI automatically clears MPIE to 0,
generates RXI and ERI interrupts (if the TIE and RIE bits in the SCSCR are set to
1), and allows the FER and ORER bits to be set.
(Initial value)
(Initial value)
(Initial value)
1, the