D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 434

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2—Address Error Flag Bit (AE): Indicates that an address error occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU
cannot write 1 to this bit. This bit can only be cleared by writing 0 after reading 1.
Bit 2: AE
0
1
Bit 1—NMI Flag Bit (NMIF): Indicates that an NMI interrupt occurred. This bit is set regardless
of whether the DMAC is in the operating or halted state. The CPU cannot write 1 to this bit. Only
0 can be written to clear this bit after 1 is read.
Bit 1: NMIF
0
1
Bit 0—DMA Master Enable Bit (DME): Enables or disables DMA transfers on all channels. If
the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is
enabled on the corresponding channel. If this bit is cleared during transfer, transfer on all the
channels will be terminated.
Even if the DME bit is set, transfer is not enabled if the TE bit is 1 or the DE bit is 0 in CHCR, or
the NMIF bit is 1 in DMAOR.
Bit 0: DME
0
1
Rev. 5.0, 09/03, page 386 of 806
Description
No DMAC address error; DMA transfer is enabled
Clearing conditions: Writing 0 to AE after reading AE = 1
DMAC address error; DMA transfer is disabled
This bit is set by occurrence of a DMAC address error
Description
No NMI input; DMA transfer is enabled
Clearing conditions: Writing 0 to NMIF after reading NMIF = 1
NMI input; DMA transfer is disabled
This bit is set by occurrence of an NMI interrupt
Description
DMA transfer disabled on all channels
DMA transfer enabled on all channels
Power-on reset, manual reset
Power-on reset, manual reset
(Initial value)
(Initial value)
(Initial value)