D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 247

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.3
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that specifies (1) CPU
cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size
in the break conditions of channel A. BBRA is initialized to H'0000 by a power-on reset.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Select a CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Note: * Don’t care
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Select an instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1
0
*
1
Bit 5: IDA1
0
1
Initial value:
Initial value:
Break Bus Cycle Register A (BBRA)
R/W:
R/W:
Bit:
Bit:
Bit 6: CDA0
0
1
0
Bit 4: IDA0
0
1
0
1
CDA1
R/W
15
—
R
0
7
0
CDA0
R/W
14
—
R
0
6
0
Description
Condition comparison is not performed
Break condition is CPU cycle
Break condition is DMAC cycle
Description
Condition comparison is not performed
Break condition is instruction fetch cycle
Break condition is data access cycle
Break condition is instruction fetch cycle or data access cycle
IDA1
R/W
13
—
R
0
5
0
IDA0
R/W
12
—
R
0
4
0
RWA1
R/W
11
—
R
0
3
0
Rev. 5.0, 09/03, page 199 of 806
RWA0
R/W
10
—
R
0
2
0
SZA1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
SZA0
R/W
—
R
8
0
0
0