D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 158

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.5
There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial
page write.
3.5.1
A TLB miss exception occurs when the virtual address and the address array of the selected TLB
entry are compared and no match is found. TLB miss exception handling includes both hardware
and software operations.
Hardware Operations: In a TLB miss, the SH7729R hardware executes a set of prescribed
operations, as follows:
1. The VPN field of the virtual address causing the exception is written to the PTEH register.
2. The virtual address causing the exception is written to the TEA register.
3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
4. The PC value indicating the address of the instruction in which the exception occurred is
5. The contents of the status register (SR) at the time of the exception are written to the saved
6. The mode (MD) bit in SR is set to 1 to place the SH7729R in privileged mode.
7. The block (BL) bit in SR is set to 1 to mask any further exception requests.
8. The register bank (RB) bit in SR is set to 1.
9. The random counter (RC) field in the MMU control register (MMUCR) is incremented by 1
10. Execution branches to the address obtained by adding the value of the VBR contents and
Software (TLB Miss Handler) Operations: The software searches the page tables in external
memory and allocates the required page table entry. Upon retrieving the required page table entry,
software must execute the following operations:
1. Write the value of the physical page number (PPN) field and the protection key (PR), page size
Rev. 5.0, 09/03, page 110 of 806
EXPEVT register.
written to the saved program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to SPC.
status register (SSR).
when all ways are checked for the TLB entry corresponding to the virtual address at which the
exception occurred, and all ways are valid. If one or more ways are invalid, those ways are set
in RC in prioritized order from way 0 through way 1, way 2, and way 3.
H'00000400 to invoke the user-written TLB miss exception handler.
(SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry
recorded in the address translation table in external memory into the PTEL register in the
SH7729R.
MMU Exceptions
TLB Miss Exception