D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 184

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 5.0, 09/03, page 136 of 806
Unconditional trap
Illegal general instruction exception
Operations: The virtual address (32 bits) that caused the exception is set in TEA. PC and
SR of the instruction that generated the exception are saved to SPC and SSR, respectively.
If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred
during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs to PC
MMU Exception, for more information.
Conditions: TRAPA instruction executed
Operations: The exception is a processing-completion type, so PC of the instruction after
the TRAPA instruction is saved to SPC. SR from the time when the TRAPA instruction
was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is
quadrupled and set in TRA (9–0). H'160 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC = VBR + H'0100.
Conditions:
a. When undefined code not in a delay slot is decoded
b. When a privileged instruction not in a delay slot is decoded in user mode
c. When a DSP instruction not in a delay slot is decoded without DSP extension
d. When an instruction that rewrites PC/SR/RS/RE in the last three instructions of repeat
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instruction: H'Fxxx
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
(SR.DSP=0)
DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,
loop is decoded.
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE,
Instructions that rewrite SR: LDC Rm, SR, LDC.L @Rm+, SR, SETRC
Instructions that rewrite RS: LDC Rm, RS, LDC.L @Rm+, RS, LDRS
Instructions that rewrite RE: LDC Rm, RE, LDC.L @Rm+, RE, LDRE
VBR + H'0100. See section 3.5.5, Processing Flow in Event of
DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1,
Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm,
RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,
STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn,
LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx
BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR,
LDC.L @Rm+, SR