D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 169

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.6.3
Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s
V bit. R0 specifies the write data and R1 specifies the address.
Reading the Data of a Specific Entry: This example reads the data section of a specific TLB
entry. The data is read in the bit order indicated in the data field in figure 3.15 (2) is read. R0
specifies the address and the data section of a selected entry is read to R1.
3.7
Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC
@Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB
instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or
P2 space).
; R0=H'1547 381C
; MMUCR.IX=0
; VPN(31–17)=B'0001 0101 0100 011
; corresponding entry association is made from the entry selected by
; the VPN(16–12)=B'1 0011 index, the V bit of the hit way is cleared to
; 0,achieving invalidation.
MOV.L
; R1 H'F300 4300
; MOV.L @R0,R1
Usage Examples
Usage Note
R0,@R1
R1=H'F201 30
VPN(16-12)=B'00100
VPN(11–10)=B'10
Way 3
Rev. 5.0, 09/03, page 121 of 806
ASID=B'0001 1100