D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 199

IC SUPER H MPU ROMLESS 208QFP

D6417729RHF200BV

Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417729RHF200BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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5.3.5
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is accessed, the latest data may be in a write-back mode
cache, so invalidate the entry that includes the latest data in the cache, generate a write-back, and
update the data in memory before using it. When the caching area is updated by a device other
than the SH7729R, invalidate the entry that includes the updated data in the cache.
5.4
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions in the privileged mode. The cache is mapped onto the P4 area in virtual address
space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data
array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size
for the address array and data array, and instruction fetches cannot be performed.
5.4.1
The address array is mapped to H'F0000000 to H'F0FFFFFF. The 32-bit address field (for
read/write accessed) and 32-bit data field (for write access) must be specified to access an element
of the address array. The address field specifies information that selects the entry to be accessed;
the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array
(figure 5.6 (1)).
In the address field, specify the entry's address in bits 11-4 to select the entry, W in bits 13-12 to
select the way, the A bit (bit 3) to specify an associative operation, and H'F0 in bits 31-24 to
indicate access to the address array. Settings for the W bits (13-12) are as follows: 00 is way 0, 01
is way 1, 10 is way 2, and 11 is way 3.
In the data field, specify the tag address in bits 31-10, LRU in bits 9-4, U bit in bit 1, and V bit in
bit 0. The upper 3 bits (bit 31-29) of the tag address must always be 0.
The following three operations on the address array are possible.
(1) Address Array Read
Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address
and w`ay that were specified in the address field. No associative operation will be performed,
regardless of the value of the associative bit (the A bit).
(2) Address Array Write (without Associative Operation)
Writes the tag address, LRU, U bit, and V bit specified in the data field to the entry that
corresponds to the entry address and way that were specified in the address field. The associative
bit (A bit) of the address field must be set to 0. An attempt to write to a cache line for which both
the U bit and V bit are set results in a write-back for that cache line. The tag address, LRU, U bit,
Coherency of Cache and External Memory
Memory-Mapped Cache
Address Array
Rev. 5.0, 09/03, page 151 of 806

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