D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 23

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.6
Section 5 Cache
5.1
5.2
5.3
5.4
5.5
Section 6 X/Y Memory
6.1
6.2
6.3
6.4
Section 7 Interrupt Controller (INTC)
7.1
7.2
Cautions............................................................................................................................. 140
Overview ........................................................................................................................... 143
5.1.1
5.1.2
5.1.3
Register Descriptions......................................................................................................... 145
5.2.1
5.2.2
Cache Operation ................................................................................................................ 148
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Memory-Mapped Cache.................................................................................................... 151
5.4.1
5.4.2
Usage Examples ................................................................................................................ 154
5.5.1
5.5.2
5.5.3
Overview ........................................................................................................................... 157
6.1.1
X/Y Memory Access from CPU........................................................................................ 158
X/Y Memory Access from DSP ........................................................................................ 160
X/Y Memory Access from DMAC ................................................................................... 160
Overview ........................................................................................................................... 161
7.1.1
7.1.2
7.1.3
7.1.4
Interrupt Sources ............................................................................................................... 165
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Features ................................................................................................................ 143
Write Access ........................................................................................................ 150
Invalidating a Specific Entry ................................................................................ 154
Invalidating a Specific Address............................................................................ 155
Reading the Data of a Specific Entry ................................................................... 155
Features ................................................................................................................ 157
Features ................................................................................................................ 161
Pin Configuration ................................................................................................. 163
Cache Structure .................................................................................................... 143
Register Configuration ......................................................................................... 145
Cache Control Register (CCR) ............................................................................. 145
Cache Control Register 2 (CCR2) ........................................................................ 146
Searching the Cache ............................................................................................. 148
Read Access ......................................................................................................... 150
Write-Back Buffer................................................................................................ 150
Coherency of Cache and External Memory.......................................................... 151
Address Array ...................................................................................................... 151
Data Array ............................................................................................................ 152
Block Diagram ..................................................................................................... 162
Register Configuration ......................................................................................... 164
NMI Interrupt ....................................................................................................... 165
IRQ Interrupts ...................................................................................................... 165
IRL Interrupts ....................................................................................................... 166
PINT Interrupts .................................................................................................... 168
On-Chip Peripheral Module Interrupts................................................................. 168
.................................................................................................................... 143
...................................................................................................... 157
........................................................................... 161
Rev. 5.0, 09/03, page xxi of xlvi