D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 223

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
7.3.1
Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which
priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These
registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in
standby mode.
Table 7.7 lists the relationship between the interrupt sources and the IPRA—IPRE bits.
Table 7.7
Note: * Always read as 0. Only 0 should be written.
As shown in table 7.7, on-chip peripheral module, IRQ, or PINT interrupts are assigned to four 4-
bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to
0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking
is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA–IPRE to H'0000.
Register
IPRA
IPRB
IPRC
IPRD
IPRE
Initial value:
Initial value:
INTC Registers
Interrupt Priority Registers A to E (IPRA–IPRE)
Interrupt Request Sources and IPRA–IPRE
R/W:
R/W:
Bit:
Bit:
Bits 15 to 12
TMU0
WDT
IRQ3
PINT0 to PINT7
DMAC
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Bits 11 to 8
TMU1
REF
IRQ2
PINT8 to PINT15
IrDA
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
Bits 7 to 4
TMU2
SCI0
IRQ1
IRQ5
SCIF
R/W
R/W
11
0
3
0
Rev. 5.0, 09/03, page 175 of 806
R/W
R/W
10
0
2
0
Bits 3 to 0
RTC
Reserved *
IRQ0
IRQ4
ADC
R/W
R/W
9
0
1
0
R/W
R/W
8
0
0
0