D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 297

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.1
The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down
modes. The watchdog timer (WDT) is a single-channel timer that counts the clock settling time
and is used when clearing standby mode and temporary standbys, such as frequency changes. It
can also be used as an ordinary watchdog timer or interval timer.
10.1.1
The CPG has the following features:
The WDT has the following features:
Four clock modes: Selection of four clock modes for different frequency ranges, power
consumption, direct crystal input, and external clock input.
Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I ); a
peripheral clock (P ) for the on-chip peripheral modules; and a bus clock (CKIO) for the
external bus interface.
Frequency change function: Internal and peripheral clock frequencies can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
Power-down mode control: The clock can be stopped for sleep mode and standby mode and
specific modules can be stopped using the module standby function.
Can be used to ensure the clock settling time: Use the WDT to cancel standby mode and the
temporary standbys which occur when the clock frequency is changed.
Can switch between watchdog timer mode and interval timer mode.
Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
Selection of power-on reset or manual reset.
Generates interrupts in interval timer mode: Internal timer interrupts occur after counter
overflow.
Selection of eight counter input clocks. Eight clocks ( 1 to 1/4096) can be obtained by
dividing the peripheral clock.
Overview
Features
Section 10 On-Chip Oscillation Circuits
Rev. 5.0, 09/03, page 249 of 806