D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 389

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
H'00000000
RTCSR.CKS(2−0)
Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2-0 in
RTCSR, and the value set in RTCOR. The value of bits CKS2-0 in RTCOR should be set so as
to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the
settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2-
CKS0 setting. When the clock is selected by CKS2-CKS0, RTCNT starts counting up from the
value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the
two values are the same, a refresh request is generated and an auto-refresh is performed. At the
same time, RTCNT is cleared to zero and the count-up is restarted. Figure 11.26 shows the
auto-refresh cycle timing.
All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr
cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new
command output cannot be performed for the duration of the number of cycles specified by the
TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS
and TPC bits must be set so as to satisfy the synchronous DRAM refresh cycle time stipulation
(active/active command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual
reset.
RTCNT
CMF
External bus
RTCOR value
CMF flag cleared by start of
refresh cycle
= 000
Figure 11.25 Auto-Refresh Operation
≠ 000
RTCNT cleared to 0 when
RTCNT = RTCOR
Auto-refresh cycle
Rev. 5.0, 09/03, page 341 of 806
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