D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 52

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
User break
controller (UBC)
Bus state
controller (BSC)
User debugging
Interface (UDI)
Timer (TMU)
Realtime clock
(RTC)
Serial communi-
cation interface 0
(SCI0)
Serial communi-
cation interface 1
(SCI1)
Rev. 5.0, 09/03, page 4 of 806
Features
Two break channels
Addresses, data values, type of access, and data size can all be set as break
conditions
Supports a sequential break function
Physical address space divided into six areas (area 0, areas 2 to 6), each a
maximum of 64 Mbytes, with the following features settable for each area:
Synchronous DRAM refresh function
Synchronous DRAM burst access function
Big or little endian can be set
E10A emulator support
JTAG-compliant
Realtime branch trace
1-kbyte on-chip RAM for fast emulation program execution
3-channel auto-reload-type 32-bit timer
Input capture function
Selection of six counter input clocks
Maximum resolution: 2 MHz
Built-in clock, calendar functions, and alarm functions
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Asynchronous mode or clock synchronous mode can be selected
Full-duplex communication
Supports smart card interface
16-byte FIFO for transmission/reception
DMA transfer capability
IrDA: interface based on 1.0
Bus size (8, 16, or 32 bits)
Number of wait cycles (also supports a hardware wait function)
Specifying the memory to be connected to each area enables direct
connection to SRAM, DRAM, synchronous DRAM, and burst ROM
Supports PCMCIA interface (2 channels)
Outputs chip select signal (CS0, CS2–CS6) for corresponding area
Programmable refresh interval
Supports self-refresh mode