D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 122

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 2.26 Added CPU System Control Instructions
Instruction
SETRC #imm
SETRC Rn
LDRS
LDRE
STC
STC
STC
STS
STS
STS
STS
STS
STS
STS.L DSR,@-Rn
STS.L A0,@-Rn
STS.L X0,@-Rn
STS.L X1,@-Rn
STS.L Y0,@-Rn
STS.L Y1,@-Rn
STC.L MOD,@-Rn
STC.L RS,@-Rn
STC.L RE,@-Rn
LDS.L @Rn+,DSR
LDS.L @Rn+,A0
LDS.L @Rn+,X0
LDS.L @Rn+,X1
LDS.L @Rn+,Y0
LDS.L @Rn+,Y1
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
Rev. 5.0, 09/03, page 74 of 806
@(disp,PC)
@(disp,PC)
MOD,Rn
RS,Rn
RE,Rn
DSR,Rn
A0,Rn
X0,Rn
X1,Rn
Y0,Rn
Y1,Rn
Instruction Code
10000010iiiiiiii imm
0100nnnn00010100 Rn[11:0]
10001100dddddddd (disp 2 + PC)
10001110dddddddd (disp 2 + PC)
0000nnnn01010010 MOD
0000nnnn01100010 RS
0000nnnn01110010 RE
0000nnnn01101010 DSR
0000nnnn01111010 A0
0000nnnn10001010 X0
0000nnnn10011010 X1
0000nnnn10101010 Y0
0000nnnn10111010 Y1
0100nnnn01100010 Rn – 4
0100nnnn01110010 Rn – 4
0100nnnn10000010 Rn – 4
0100nnnn10010010 Rn – 4
0100nnnn10100010 Rn – 4
0100nnnn10110010 Rn – 4
0100nnnn01010011 Rn – 4
0100nnnn01100011 Rn – 4
0100nnnn01110011 Rn – 4
0100nnnn01100110 (Rn)
0100nnnn01110110 (Rn)
0100nnnn10000110 (Rn)
0100nnnn10010110 (Rn)
0100nnnn10100110 (Rn)
0100nnnn10110110 (Rn)
0100nnnn01010111 (Rn)
0100nnnn01100111 (Rn)
Operation
Rn
Rn
Rn
Rn
Rn
Rn
Rn
RC (of SR)
DSR, Rn + 4
A0, Rn + 4
X0, Rn + 4
X1, Rn + 4
Y0, Rn + 4
Y1, Rn + 4
MOD, Rn + 4
RS, Rn + 4
Rn
Rn
Rn, DSR
Rn, A0
Rn, X0
Rn, X1
Rn, Y0
Rn, Y1
Rn, MOD
Rn, RS
Rn, RE
R C (of SR)
RS
RE
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
(Rn)
Rn
Rn
Rn
Rn
Rn
(Rn)
Rn
(Rn)
Rn
Rn
Execu-
tion
States
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
5
5
T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—