D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 160

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.5.3
A TLB invalid exception occurs when the virtual address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
handling includes both hardware and software operations.
Hardware Operations: In a TLB invalid exception, the SH7729R hardware executes a set of
prescribed operations, as follows:
1. The VPN number of the virtual address causing the exception is written to the PTEH register.
2. The virtual address causing the exception is written to the TEA register.
3. The way number causing the exception is written to RC in MMUCR.
4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
5. The PC value indicating the address of the instruction in which the exception occurred is
6. The contents of SR at the time of the exception are written to SSR.
7. The mode (MD) bit in SR is set to 1 to place the SH7729R in privileged mode.
8. The block (BL) bit in SR is set to 1 to mask any further exception requests.
9. The register bank (RB) bit in SR is set to 1.
10. Execution branches to the address obtained by adding the value of the VBR contents and
Software (TLB Invalid Exception Handler) Operations: The software searches the page tables
in external memory and assigns the required page table entry. Upon retrieving the required page
table entry, software must execute the following operations:
1. Write the values of the physical page number (PPN) field and the values of the protection key
2. If using software for way selection for entry replacement, write the desired value to the RC
3. Issue an LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
4. Issue an RTE instruction to terminate the handler and return to the instruction stream. The RTE
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EXPEVT register.
written to SPC. If the exception occurred in a delay slot, the PC value indicating the address of
the delayed branch instruction is written to SPC.
H'00000100, and the TLB protection violation exception handler starts.
(PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page
table entry recorded in the external memory to the PTEL register.
field in MMUCR.
instruction should be issued after two LDTLB instructions.
TLB Invalid Exception