D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 438
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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source of the transfer request does not have to be the data transfer source or destination. When
RXI is set as the transfer request, however, the transfer source must be the SCI's receive data
register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the
SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the data transfer
source must be the A/D data register.
Table 12.4 Selecting On-Chip Peripheral Module Request Modes with RS Bits
RS3 RS2 RS1 RS0
1
1
1
1
1
1
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip peripheral module (excluding
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not sent to the CPU.
The DMA transfer request signals in table 12.4 are automatically discontinued when the
corresponding DMA transfer is performed. If cycle-steal mode is being employed, they are
withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last
transfer.
Rev. 5.0, 09/03, page 390 of 806
0
0
1
1
1
1
DMAC, BSC, UBC)
1
1
0
0
1
1
0
1
0
1
0
1
DMA
Transfer
Request
Source
IrDA
transmitter
IrDA
receiver
SCIF
transmitter
SCIF
receiver
A/D
converter
CMT
DMA Transfer Request Signal Source
TXI1 (IrDA transmit-data-empty
interrupt transfer request)
RXI1 (IrDA receive-data-full
interrupt transfer request)
TXI2 (SCIF transmit-data-empty
interrupt transfer request)
RXI2 (SCIF receive-data-full
interrupt transfer request)
ADI (A/D conversion end
interrupt)
CMI (Compare match timer
interrupt)
Any *
RDR1
Any *
RDR1
ADDR
Any *
Desti-
nation Bus Mode
TDR1
Any *
TDR2
Any *
Any *
Any *
Cycle-steal
Cycle-steal
Cycle-steal
Cycle-steal
Cycle-steal
Burst/
cycle-steal
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