LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 97

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 73.
UM10360
User manual
Symbol
P0[20] / DTR1 /
SCL1
P0[21] / RI1 / RD1
P0[22] / RTS1 / TD1 56
P0[23] / AD0[0] /
I2SRX_CLK /
CAP3[0]
P0[24] / AD0[1] /
I2SRX_WS /
CAP3[1]
P0[25] / AD0[2] /
I2SRX_SDA /
TXD3
P0[26] / AD0[3] /
AOUT / RXD3
P0[27] / SDA0 /
USB_SDA
Pin description
LQFP
100
58
57
9
8
7
6
25
…continued
LQFP
80
-
-
44
-
-
7
6
-
Type Description
I/O
O
I/O
I/O
I
I
I/O
O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
I
O
I
I/O
I/O
I/O
All information provided in this document is subject to legal disclaimers.
P0[20] — General purpose digital input/output pin.
DTR1 — Data Terminal Ready output for UART1. Can also be configured
to be an RS-485/EIA-485 output enable signal.
SCL1 — I
pad, see
P0[21] — General purpose digital input/output pin.
RI1 — Ring Indicator input for UART1.
RD1 — CAN1 receiver input.
P0[22] — General purpose digital input/output pin.
RTS1 — Request to Send output for UART1. Can also be configured to be
an RS-485/EIA-485 output enable signal.
TD1 — CAN1 transmitter output.
P0[23] — General purpose digital input/output pin. When configured as an
ADC input, digital section of the pad is disabled.
AD0[0] — A/D converter 0, input 0.
I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
CAP3[0] — Capture input for Timer 3, channel 0.
P0[24] — General purpose digital input/output pin. When configured as an
ADC input, digital section of the pad is disabled.
AD0[1] — A/D converter 0, input 1.
I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
specification .
CAP3[1] — Capture input for Timer 3, channel 1.
P0[25] — General purpose digital input/output pin. When configured as an
ADC input, digital section of the pad is disabled.
AD0[2] — A/D converter 0, input 2.
I2SRX_SDA — Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I
TXD3 — Transmitter output for UART3.
P0[26] — General purpose digital input/output pin. When configured as an
ADC input or DAC output, the digital section of the pad is disabled.
AD0[3] — A/D converter 0, input 3.
AOUT — D/A converter output.
RXD3 — Receiver input for UART3.
P0[27] — General purpose digital input/output pin. Open-drain 5 V tolerant
digital I/O pad, compatible with I
mode, 400 kHz Fast Mode, and 1 MHz Fast Mode Plus. This pad requires
an external pull-up to provide output functionality. When power is switched
off, this pin connected to the I
I
SDA0 — I
Section 19.1
USB_SDA — USB port I
2
Rev. 2 — 19 August 2010
C lines. Open-drain configuration applies to all functions on this pin.
Section 19.1
2
2
C1 clock input/output (this pin does not use a specialized I2C
C0 data input/output (this pin uses a specialized I2C pad, see
for details).
for details).
2
C serial data (OTG transceiver).
2
Chapter 7: LPC17xx Pin configuration
C-bus is floating and does not disturb the
2
C-bus specifications for 100 kHz standard
2
S bus specification .
2
S bus specification .
UM10360
© NXP B.V. 2010. All rights reserved.
2
S bus
97 of 840