LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 462
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 402. Miscellaneous States
UM10360
User manual
Status
Code
(I2CSTAT)
0xF8
0x00
19.9.6.1 I2STAT = 0xF8
19.9.6.2 I2STAT = 0x00
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
19.9.7.1 Simultaneous repeated START conditions from two masters
19.9.6 Miscellaneous states
19.9.7 Some special cases
2
There are two I2STAT codes that do not correspond to a defined I
Table
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
is not involved in a serial transfer.
This status code indicates that a bus error has occurred during an I
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
causes the I
clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
A repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
repeated START condition (see
either master since they were both transmitting the same data.
C block
2
C-bus
2
402). These are discussed below.
C hardware has facilities to handle the following special cases that may occur
Application software response
To/From I2DAT
No I2DAT action
No I2DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
To I2CON
STA STO SI
0
No I2CON action
Figure
1
97). Until this occurs, arbitration is not lost by
0
2
C block signals. When a bus error occurs, SI is
AA
X
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
Chapter 19: LPC17xx I2C0/1/2
2
C hardware state (see
2
C serial transfer. A
UM10360
© NXP B.V. 2010. All rights reserved.
2
C hardware
2
462 of 840
C block
2
C
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