LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 256

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 30. UDCA Head register and DMA Descriptors
UDCA HEAD
REGISTER
11.15.3 Triggering the DMA engine
11.15.4 The DMA descriptor
UDCA
DDP-EP16
DDP-EP31
An endpoint raises a DMA request when Slave mode is disabled by setting the
corresponding bit in the USBEpIntEn register to 0
interrupt occurs (see
- 0x5000
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found for
the endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint
number is processed first.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section
DMA transfers are described by a data structure called the DMA Descriptor (DD).
DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at
word-aligned addresses.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
The parameters associated with a DMA transfer are:
DDP-EP2
•
The start address of the DMA buffer
11.12.3).
C250)”).
0
1
2
16
31
All information provided in this document is subject to legal disclaimers.
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Section 11.10.7.1 “USB DMA Request Status register (USBDMARSt
Rev. 2 — 19 August 2010
Next_DD_pointer
Next_DD_pointer
DD-EP16-a
DD-EP2-a
Chapter 11: LPC17xx USB device controller
Next_DD_pointer
Next_DD_pointer
DD-EP16-b
DD-EP2-b
(Section
11.10.3.2) and an endpoint
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Next_DD_pointer
DD-EP2-c
UM10360
© NXP B.V. 2010. All rights reserved.
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