LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 487

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 107. Typical receiver master mode, with or without MCLK output
Fig 108. Receiver master mode sharing the transmitter reference clock
Fig 109. 4-wire receiver master mode sharing the transmitter bit clock and WS
Fig 110. Typical receiver slave mode
Fig 111. Receiver slave mode sharing the transmitter reference clock
I2S_PCLK
I2SRX_RATE[15:8]
I2SRX_RATE[7:0]
Rate Divider
Fractional
X
8-bit
TX_REF
TX_REF
RX_REF
Y
I2SRXBITRATE[5:0]
I2SRXBITRATE[5:0]
I2SRXBITRATE[5:0]
÷2
TX bit clock
(1 to 64)
(1 to 64)
(1 to 64)
÷N
÷N
÷N
All information provided in this document is subject to legal disclaimers.
RX_REF
RX bit clock
RX bit clock
RX bit clock
I2SRXBITRATE[5:0]
peripheral
Rev. 2 — 19 August 2010
(receive)
(1 to 64)
block
I
÷N
2
S
peripheral
(receive)
peripheral
peripheral
(receive)
(receive)
RX bit clock
block
block
TX_WS ref
block
I
2
I
I
S
2
2
S
S
RX_WS ref
peripheral
(receive)
block
I2SRX_CLK
I2SRX_SDA
I2SRX_WS
I
2
S
I2SRXMODE[3]
RX_WS ref
I2SRX_CLK
I2SRX_SDA
I2SRX_WS
I2SRX_CLK
I2SRX_SDA
I2SRX_WS
I2SRX_SDA
I2SRX_WS
Chapter 20: LPC17xx I2S
(Pin OE)
UM10360
I2SRX_MCLK
I2SRX_CLK
I2SRX_SDA
I2SRX_WS
© NXP B.V. 2010. All rights reserved.
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