LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 808

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 285: UARTn Fractional Divider Register (U0FDR -
Table 286. Fractional Divider setting look-up table . . . . .315
Table 287: UARTn Transmit Enable Register (U0TER -
Table 288: UART1 Pin Description . . . . . . . . . . . . . . . . .319
Table 289: UART1 register map . . . . . . . . . . . . . . . . . . .320
Table 290: UART1 Receiver Buffer Register (U1RBR -
Table 291: UART1 Transmitter Holding Register (U1THR -
Table 292: UART1 Divisor Latch LSB Register (U1DLL -
Table 293: UART1 Divisor Latch MSB Register (U1DLM -
Table 294: UART1 Interrupt Enable Register (U1IER -
Table 295: UART1 Interrupt Identification Register (U1IIR -
Table 296: UART1 Interrupt Handling . . . . . . . . . . . . . . .324
Table 297: UART1 FIFO Control Register (U1FCR - address
Table 298: UART1 Line Control Register (U1LCR - address
Table 299: UART1 Modem Control Register (U1MCR -
Table 300: Modem status interrupt generation . . . . . . . .328
Table 301: UART1 Line Status Register (U1LSR - address
Table 302: UART1 Modem Status Register (U1MSR -
Table 303: UART1 Scratch Pad Register (U1SCR - address
Table 304: Auto-baud Control Register (U1ACR - address
Table 305: UART1 Fractional Divider Register (U1FDR -
Table 306. Fractional Divider setting look-up table . . . . .337
Table 307: UART1 Transmit Enable Register (U1TER -
Table 308: UART1 RS485 Control register (U1RS485CTRL -
Table 309. UART1 RS-485 Address Match register
Table 310. UART1 RS-485 Delay value register
Table 311. CAN Pin descriptions . . . . . . . . . . . . . . . . . . .344
Table 312. Memory map of the CAN block . . . . . . . . . . .349
Table 313. CAN acceptance filter and central CAN registers
UM10360
User manual
address 0x4000 C028, U2FDR - 0x4009 8028,
U3FDR - 0x4009 C028) bit description. . . . . .312
address 0x4000 C030, U2TER - 0x4009 8030,
U3TER - 0x4009 C030) bit description . . . . . .316
address 0x4001 0000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .321
address 0x4001 0000 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .321
address 0x4001 0000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .322
address 0x4001 0004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .322
address 0x4001 0004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .322
address 0x4001 0008) bit description. . . . . . .323
0x4001 0008) bit description . . . . . . . . . . . . .325
0x4001 000C) bit description . . . . . . . . . . . . .326
address 0x4001 0010) bit description. . . . . . .327
0x4001 0014) bit description . . . . . . . . . . . . .329
address 0x4001 0018) bit description. . . . . . .330
0x4001 0014) bit description . . . . . . . . . . . . .331
0x4001 0020) bit description . . . . . . . . . . . . .331
address 0x4001 0028) bit description. . . . . . .335
address 0x4001 0030) bit description. . . . . . .338
address 0x4001 004C) bit description . . . . . .338
(U1RS485ADRMATCH - address 0x4001 0050)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .339
(U1RS485DLY - address 0x4001 0054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .339
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 314. CAN1 and CAN2 controller register map . . . 349
Table 315. CAN1 and CAN2 controller register summary351
Table 316. CAN Wake and Sleep registers. . . . . . . . . . . 351
Table 317. CAN Mode register (CAN1MOD - address
Table 318. CAN Command Register (CAN1CMR - address
Table 319. CAN Global Status Register (CAN1GSR -
Table 320. CAN Interrupt and Capture Register (CAN1ICR -
Table 321. CAN Interrupt Enable Register (CAN1IER -
Table 322. CAN Bus Timing Register (CAN1BTR - address
Table 323. CAN Error Warning Limit register (CAN1EWL -
Table 324. CAN Status Register (CAN1SR - address
Table 325. CAN Receive Frame Status register (CAN1RFS -
Table 326. CAN Receive Identifier register (CAN1RID -
Table 327. RX Identifier register when FF = 1 . . . . . . . . 366
Table 328. CAN Receive Data register A (CAN1RDA -
Table 329. CAN Receive Data register B (CAN1RDB -
Table 330. CAN Transmit Frame Information register
Table 331. CAN Transfer Identifier register (CAN1TID[1/2/3]
Table 332. Transfer Identifier register when FF = 1 . . . . 369
Table 333. CAN Transmit Data register A (CAN1TDA[1/2/3] -
Table 334. CAN Transmit Data register B (CAN1TDB[1/2/3] -
Table 335. CAN Sleep Clear register (CANSLEEPCLR -
349
0x4004 4000, CAN2MOD - address
0x4004 8000) bit description . . . . . . . . . . . . . 352
0x4004 4004, CAN2CMR - address 0x4004 8004)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 353
address 0x4004 4008, CAN2GSR - address
0x4004 8008) bit description . . . . . . . . . . . . . 355
address 0x4004 400C, CAN2ICR - address
0x4004 800C) bit description . . . . . . . . . . . . . 357
address 0x4004 4010, CAN2IER - address
0x4004 8010) bit description . . . . . . . . . . . . . 360
0x4004 4014, CAN2BTR - address 0x4004 8014)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 361
address 0x4004 4018, CAN2EWL - address
0x4004 8018) bit description . . . . . . . . . . . . . 363
0x4004 401C, CAN2SR - address 0x4004 801C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 363
address 0x4004 4020, CAN2RFS - address
0x4004 8020) bit description . . . . . . . . . . . . . 365
address 0x4004 4024, CAN2RID - address
0x4004 8024) bit description . . . . . . . . . . . . . 366
address 0x4004 4028, CAN2RDA - address
0x4004 8028) bit description . . . . . . . . . . . . . 366
address 0x4004 402C, CAN2RDB - address
0x4004 802C) bit description . . . . . . . . . . . . . 366
(CAN1TFI[1/2/3] - address 0x4004 40[30/40/50],
CAN2TFI[1/2/3] - 0x4004 80[30/40/50]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
- address 0x4004 40[34/44/54], CAN2TID[1/2/3] -
address 0x4004 80[34/44/54]) bit description 368
address 0x4004 40[38/48/58], CAN2TDA[1/2/3] -
address 0x4004 80[38/48/58]) bit description 369
address 0x4004 40[3C/4C/5C], CAN2TDB[1/2/3] -
address 0x4004 80[3C/4C/5C]) bit description . .
369
address 0x400F C110) bit description . . . . . . 370
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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