LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 260
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
11.15.5.1 Setting up DMA transfers
11.15.5.2 Finding DMA Descriptor
11.15.5.3 Transferring the data
11.15.5.4 Optimizing descriptor fetch
11.15.5 Non-isochronous endpoint operation
Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled
for DMA transfer. These DDs are present in on-chip RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the USBEpDMAEn register
is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in
Table
DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).
When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first
determine whether a new descriptor has to the fetched or not. A new descriptor does not
have to be fetched if the last packet transferred was for the same endpoint and the DD is
not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this
condition (see
If a new descriptor has to be read, the DMA engine will calculate the location of the DDP
for this endpoint and will fetch the start address of the DD from this location. A DD start
address at location zero is considered invalid. In this case the NDDR interrupt is raised.
All other word-aligned addresses are considered valid.
When the DD is fetched, the DD status word (word 3) is read first and the status of the
DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the
DMA engine will read the control word (word 1) of the DD.
If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)
of the DD and load it to the DDP. The new DDP is written to the UDCA area.
The full DD (4 words) will then be fetched from the address in the DDP. The DD will give
the details of the DMA transfer to be done. The DMA engine will load its hardware
resources with the information fetched from the DD (start address, DMA count etc.).
If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR
interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.
For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and
transferred to on-chip RAM memory locations starting from DMA_buffer_start_addr. For
IN endpoints, the data is fetched from on-chip RAM at DMA_buffer_start_addr and written
to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are updated
after each packet is transferred.
A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a
new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet
transfer, hardware sets an internal flag called DMA_PROCEED.
251.
Section 11.15.5.4 “Optimizing descriptor fetch” on page
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
(Section
11.10.7.6).The DMA_mode bit field in the descriptor
Chapter 11: LPC17xx USB device controller
UM10360
260).
© NXP B.V. 2010. All rights reserved.
260 of 840
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