LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 828
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
17.7.7
Chapter 18: LPC17xx SSP0/1
18.1
18.2
18.3
18.4
18.5
18.5.1
18.5.2
18.5.2.1
18.5.2.2
18.5.2.3
18.5.2.4
18.5.2.5
18.5.3
18.5.3.1
18.6
Chapter 19: LPC17xx I2C0/1/2
19.1
19.2
19.3
19.4
19.4.1
19.5
19.6
19.6.1
19.6.2
19.6.3
19.6.4
19.7
19.7.1
19.7.2
19.7.3
19.7.4
19.7.5
19.7.6
19.7.7
UM10360
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 412
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 413
Bus description . . . . . . . . . . . . . . . . . . . . . . . 413
Register description . . . . . . . . . . . . . . . . . . . 421
Basic configuration . . . . . . . . . . . . . . . . . . . . 428
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 430
I
I
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 431
C implementation and operation . . . . . . . . 434
SPI Interrupt Register (S0SPINT - 0x4002
001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Texas Instruments synchronous serial frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
SPI frame format . . . . . . . . . . . . . . . . . . . . . 414
Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
SPI format with CPOL=0,CPHA=0 . . . . . . . . 415
SPI format with CPOL=0,CPHA=1 . . . . . . . . 416
SPI format with CPOL = 1,CPHA = 0 . . . . . . 416
SPI format with CPOL = 1,CPHA = 1 . . . . . . 418
National Semiconductor Microwire frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 420
I
Master Transmitter mode . . . . . . . . . . . . . . . 431
Master Receiver mode . . . . . . . . . . . . . . . . . 432
Slave Receiver mode . . . . . . . . . . . . . . . . . . 433
Slave Transmitter mode . . . . . . . . . . . . . . . . 434
Input filters and output stages. . . . . . . . . . . . 435
Address Registers, I2ADR0 to I2ADR3 . . . . 436
Address mask registers, I2MASK0 to
I2MASK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 436
Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 436
Arbitration and synchronization logic . . . . . . 436
Serial clock generator . . . . . . . . . . . . . . . . . . 437
2
C FAST Mode Plus. . . . . . . . . . . . . . . . . . . 430
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
17.8
18.6.1
18.6.2
18.6.3
18.6.4
18.6.5
18.6.6
18.6.7
18.6.8
18.6.9
18.6.10
19.7.8
19.7.9
19.7.10
19.8
19.8.1
19.8.2
19.8.3
19.8.4
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Register description . . . . . . . . . . . . . . . . . . . 439
SSPn Control Register 0 (SSP0CR0 -
0x4008 8000, SSP1CR0 - 0x4003 0000). . . 421
SSPn Control Register 1 (SSP0CR1 -
0x4008 8004, SSP1CR1 - 0x4003 0004). . . 422
SSPn Data Register (SSP0DR - 0x4008 8008,
SSP1DR - 0x4003 0008) . . . . . . . . . . . . . . . 423
SSPn Status Register (SSP0SR - 0x4008 800C,
SSP1SR - 0x4003 000C) . . . . . . . . . . . . . . . 424
SSPn Clock Prescale Register (SSP0CPSR -
0x4008 8010, SSP1CPSR - 0x4003 0010) . 424
SSPn Interrupt Mask Set/Clear Register
(SSP0IMSC - 0x4008 8014, SSP1IMSC -
0x4003 0014) . . . . . . . . . . . . . . . . . . . . . . . . 424
SSPn Raw Interrupt Status Register (SSP0RIS -
0x4008 8018, SSP1RIS - 0x4003 0018) . . . 425
SSPn Masked Interrupt Status Register
(SSP0MIS - 0x4008 801C, SSP1MIS -
0x4003 001C) . . . . . . . . . . . . . . . . . . . . . . . 425
SSPn Interrupt Clear Register (SSP0ICR -
0x4008 8020, SSP1ICR - 0x4003 0020) . . . 426
SSPn DMA Control Register (SSP0DMACR -
0x4008 8024, SSP1DMACR - 0x4003 0024) 426
Timing and control . . . . . . . . . . . . . . . . . . . . 438
Control register, I2CONSET and I2CONCLR 438
Status decoder and status register. . . . . . . . 438
I
I2C0CONSET - 0x4001 C000; I
I2C1CONSET - 0x4005 C000; I
I2C2CONSET - 0x400A 0000). . . . . . . . . . . 440
I
I2C0CONCLR - 0x4001 C018; I
I2C1CONCLR - 0x4005 C018; I
I2C2CONCLR - 0x400A 0018). . . . . . . . . . . 442
I
0x4001 C004; I
I
I
0x4001 C008; I
I
2
2
2
2
2
2
C Control Set register (I2CONSET: I
C Control Clear register (I2CONCLR: I
C Status register (I2STAT: I
C2, I2C2STAT - 0x400A 0004) . . . . . . . . . 443
C Data register (I2DAT: I
C2, I2C2DAT - 0x400A 0008) . . . . . . . . . . 443
Chapter 35: Supplementary information
2
2
C1, I2C1STAT - 0x4005 C004;
C1, I2C1DAT - 0x4005 C008;
2
C0, I2C0DAT -
UM10360
2
© NXP B.V. 2010. All rights reserved.
C0, I2C0STAT -
2
2
2
2
C1,
C2,
C1,
C2,
continued >>
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C0,
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