LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 460

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 400. Slave Receiver mode
UM10360
User manual
I2CSTAT
Status
Code
0x98
0xA0
Status of the I
and hardware
Previously addressed
with General Call; DATA
byte has been received;
NOT ACK has been
returned.
A STOP condition or
repeated START
condition has been
received while still
addressed as Slave
Receiver or Slave
Transmitter.
2
C-bus
Application software response
To/From I2DAT To I2CON
Read data byte
or
Read data byte
or
Read data byte
or
Read data byte
No STDAT
action or
No STDAT
action or
No STDAT
action or
No STDAT
action
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
STA STO SI
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
0
1
0
1
0
1
0
1
Next action taken by I
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
Switched to not addressed SLV mode;
recognition of own SLA or General Call
address. A START condition will be
transmitted when the bus becomes free.
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes
free.
Chapter 19: LPC17xx I2C0/1/2
UM10360
2
© NXP B.V. 2010. All rights reserved.
C hardware
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