LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 533

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018, 0x400B 801C, 0x400B 8020) bit description
Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028, 0x400B 802C) bit description
UM10360
User manual
Bit
31:0
Bit
31:0
Symbol
MCTC0/1/2
Symbol
MCLIM0/1/2
25.7.6.1 Match and Limit write and operating registers
25.7.6 MCPWM Limit 0-2 registers (MCLIM0-2 - 0x400B 8024, 0x400B 8028,
0x400B 802C)
These registers hold the limiting values for timer/counters 0-2. When a timer/counter
reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts
over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which
time it begins counting up again.
If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, the match
between TC and LIM switches the channel’s A output from “active” to “passive” state. If
the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously
switches the channel’s B output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s B
output switches from “passive” to “active” state.
In center-aligned mode, matches between a channel’s TC and LIM registers have no
effect on its A and B outputs.
Writing to either a Limit or a Match register loads a “write” register, and, if the channel is
stopped, it also loads a shadow “operating” register that is compared to the TC. If the
channel is running and its “disable update” bit in MCCON is 0, the operating registers are
loaded from the write registers as follows:
Reading an MCLIM register address always returns the operating value.
Simultaneous update of the Limit and Match registers can be achieved by writing the
MCLIMx and MCMATx registers and then clearing the DISUPx bits in the MCCON register
(see
cycle (also see
Remark: In timer mode, the period of a channel’s modulated MCO outputs is determined
by its Limit register, and the pulse width at the start of the period is determined by its
Match register. You can consider the Limit register to be a “Period register” and the Match
register to be a “Pulse Width register”.
1. in edge-aligned mode, when the TC matches the operating Limit register;
2. in center-aligned mode, when the TC counts back down to 0. If the channel is running
Description
Timer/Counter values for channels 0, 1, 2.
Description
Limit values for TC0, 1, 2.
and the “disable update” bit is 1, the operating registers are not loaded from the write
registers until software stops the channel.
Table
457). The simultaneous update will occur at the beginning of the next PWM
Section
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
25.8.2).
Chapter 25: LPC17xx Motor control PWM
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0xFFFF FFFF
Reset value
0
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