LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 403

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 74. SPI data transfer format (CPHA = 0 and CPHA = 1)
Cycle # CPHA = 0
Cycle # CPHA = 1
MOSI (CPHA = 0)
MISO (CPHA = 0)
MOSI (CPHA = 1)
MISO (CPHA = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
CPHA = 0
CPHA = 1
SSEL
The data and clock phase relationships are summarized in
Table 359. SPI Data To Clock Phase Relationship
The definition of when a transfer starts and stops is dependent on whether a device is a
master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on
the last clock edge where data is sampled.
CPOL and CPHA
settings
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
BIT 1
BIT 1
1
BIT 1
BIT 1
1
All information provided in this document is subject to legal disclaimers.
BIT 2
BIT 2
2
BIT 2
BIT 2
When the first data bit is
driven
Prior to first SCK rising edge
First SCK rising edge
Prior to first SCK falling edge
First SCK falling edge
2
Rev. 2 — 19 August 2010
BIT 3
BIT 3
3
BIT 3
BIT 3
3
BIT 4
BIT 4
4
BIT 4
BIT 4
4
BIT 5
BIT 5
5
BIT 5
BIT 5
5
BIT 6
BIT 6
6
When all other data
bits are driven
SCK falling edge
SCK rising edge
SCK rising edge
SCK falling edge
BIT 6
BIT 6
6
BIT 7
BIT 7
7
BIT 7
BIT 7
Table
7
BIT 8
Chapter 17: LPC17xx SPI
BIT 8
8
359.
BIT 8
BIT 8
8
UM10360
© NXP B.V. 2010. All rights reserved.
SCK falling edge
When data is
sampled
SCK rising edge
SCK falling edge
SCK rising edge
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