LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 55

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108)
Table 38.
The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 2 results in CCLK being one third of the PLL0 output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL0 output, etc.
This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in
PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock
source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB
subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the
USB clock divider.
The USBCLKCFG register controls the division of the PLL0 output before it is used by the
USB subsystem.The PLL0 output must be divided in order to bring the USB clock
frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct
USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL
operating range.
Remark: The Internal RC oscillator should not be used to drive PLL0 when the USB is
using PLL0 as a clock source because a more precise clock is needed for USB
specification compliance (see
Bit
7:0
31:8
Symbol
CCLKSEL
-
CPU Clock Configuration register (CCLKCFG - address 0x400F C104) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
2
3
4
:
255
Rev. 2 — 19 August 2010
Selects the divide value for creating the CPU clock (CCLK)
from the PLL0 output.
pllclk is divided by 1 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.
pllclk is divided by 2 to produce the CPU clock. This setting is
not allowed when the PLL0 is connected, because the rate
would always be greater than the maximum allowed CPU
clock.
pllclk is divided by 3 to produce the CPU clock.
pllclk is divided by 4 to produce the CPU clock.
pllclk is divided by 5 to produce the CPU clock.
:
pllclk is divided by 256 to produce the CPU clock.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table
17).
Chapter 4: LPC17xx Clocking and power control
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0x00
NA