LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 169

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4)
10.14.3 Interrupt Clear Register (IntClear - 0x5000 0FE8)
The interrupt status register is read-only. Setting can be done via the IntSet register. Reset
can be accomplished via the IntClear register.
The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt
enable register bit definition is shown in
Table 171. Interrupt Enable register (intEnable - address 0x5000 0FE4) bit description
The Interrupt Clear register (IntClear) is a write-only register with an address of
0x5000 0FE8. The interrupt clear register bit definition is shown in
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14 -
Symbol
RxOverrunIntEn
RxErrorIntEn
RxFinishedIntEn
RxDoneIntEn
TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor
TxErrorIntEn
TxFinishedIntEn
TxDoneIntEn
-
SoftIntEn
WakeupIntEn
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Enable for interrupt trigger on receive buffer overrun or
descriptor underrun situations.
Enable for interrupt trigger on receive errors.
Enable for interrupt triggered when all receive descriptors have
been processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Enable for interrupt triggered when a receive descriptor has
been processed while the Interrupt bit in the Control field of the
descriptor was set.
underrun situations.
Enable for interrupt trigger on transmit errors.
Enable for interrupt triggered when all transmit descriptors
have been processed i.e. on the transition to the situation
where ProduceIndex == ConsumeIndex.
Enable for interrupt triggered when a descriptor has been
transmitted while the Interrupt bit in the Control field of the
descriptor was set.
Unused
Enable for interrupt triggered by the SoftInt bit in the IntStatus
register, caused by software writing a 1 to the SoftIntSet bit in
the IntSet register.
Enable for interrupt triggered by a Wake-up event detected by
the receive filter.
Unused
Table
171.
Chapter 10: LPC17xx Ethernet
Table
UM10360
© NXP B.V. 2010. All rights reserved.
172.
169 of 840
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0