LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 102

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 73.
UM10360
User manual
Symbol
P2[12] / EINT2 /
I2STX_WS
P2[13] / EINT3 /
I2STX_SDA
P3[0] to P3[31]
P3[25] / MAT0[0] /
PWM1[2]
P3[26] / STCLK /
MAT0[1] / PWM1[3]
P4[0] to P4[31]
P4[28] /
RX_MCLK /
MAT2[0] / TXD3
P4[29] TX_MCLK /
MAT2[1] / RXD3
TDO / SWO
TDI
TMS / SWDIO
TRST
TCK / SWDCLK
RTCK
Pin description
5
LQFP
100
51
50
27
26
82
85
1
2
3
4
100
…continued
LQFP
80
-
-
-
-
65
68
1
2
3
4
5
-
Type Description
I/O
I
I/O
I/O
I
I/O
I/O
I/O
O
O
I/O
I
O
O
I/O
I/O
I
O
O
I/O
I
O
I
O
O
I
I
I/O
I
I
I
I/O
All information provided in this document is subject to legal disclaimers.
P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
EINT2 — External interrupt 2 input.
I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
specification .
P2[13] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
EINT3 — External interrupt 3 input.
I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 3 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 24, and 27 through 31 of this port are
not available.
P3[25] — General purpose digital input/output pin.
MAT0[0] — Match output for Timer 0, channel 0.
PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26] — General purpose digital input/output pin.
STCLK — System tick timer clock input.
MAT0[1] — Match output for Timer 0, channel 1.
PWM1[3] — Pulse Width Modulator 1, output 3.
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 4 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 27, 30, and 31 of this port are not
available.
P4[28] — General purpose digital input/output pin.
RX_MCLK — I
MAT2[0] — Match output for Timer 2, channel 0.
TXD3 — Transmitter output for UART3.
P4[29] — General purpose digital input/output pin.
TX_MCLK — I
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
TDO — Test Data out for JTAG interface.
SWO — Serial wire trace output.
TDI — Test Data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
SWDIO — Serial wire debug data input/output.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface.
SWDCLK — Serial wire clock.
RTCK — JTAG interface control signal.
Rev. 2 — 19 August 2010
2
2
S transmit master clock.
S receive master clock.
Chapter 7: LPC17xx Pin configuration
2
S bus specification .
UM10360
© NXP B.V. 2010. All rights reserved.
2
S bus
102 of 840