LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 246

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 243. Configure Device command bit description
Table 244. Set Mode command bit description
UM10360
User manual
Bit
0
7:1
Bit
0
1
2
3
4
5
6
7
Symbol
CONF_DEVICE
-
Symbol
AP_CLK
INAK_CI
INAK_CO
INAK_II
INAK_IO
INAK_BI
INAK_BO
-
11.12.3 Set Mode (Command: 0xF3, Data: write 1 byte)
11.12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2
[1]
[2]
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
[1]
[2]
bytes)
Returns the frame number of the last successfully received SOF. The frame number is
eleven bits wide. The frame number returns least significant byte first. In case the user is
only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
Description
Device is configured. All enabled non-control endpoints will respond. This bit is
cleared by hardware when a bus reset occurs. When set, the UP_LED signal is
driven LOW if the device is not in the suspended state (SUS=0).
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.
This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.
Description
Always PLL Clock.
USB_NEED_CLK is functional; the 48 MHz clock can be stopped when the
device enters suspend state.
USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be stopped when the
device enters suspend state.
Interrupt on NAK for Control IN endpoint.
Only successful transactions generate an interrupt.
Both successful and NAKed IN transactions generate interrupts.
Interrupt on NAK for Control OUT endpoint.
Only successful transactions generate an interrupt.
Both successful and NAKed OUT transactions generate interrupts.
Interrupt on NAK for Interrupt IN endpoint.
Only successful transactions generate an interrupt.
Both successful and NAKed IN transactions generate interrupts.
Interrupt on NAK for Interrupt OUT endpoints.
Only successful transactions generate an interrupt.
Both successful and NAKed OUT transactions generate interrupts.
Interrupt on NAK for Bulk IN endpoints.
Only successful transactions generate an interrupt.
Both successful and NAKed IN transactions generate interrupts.
Interrupt on NAK for Bulk OUT endpoints.
Only successful transactions generate an interrupt.
Both successful and NAKed OUT transactions generate interrupts.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
NA
Reset value
0
0
0
0
0
0
NA
0
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