LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 405
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
17.6.3 Slave operation
17.6.4 Exception conditions
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, if the optional read of the SPI Data Register does not take place, a write to
this register is required in order to clear the SPIF status bit.
The following sequence can be followed to set up the SPI prior to its first use as a slave.
This is typically done during program initialization.
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be a slave. This process assumes that any prior data transfer
has already completed. It is required that the system clock driving the SPI logic be at least
8X faster than the SPI.
Note: A read or write of the SPI Data Register is required in order to clear the SPIF status
bit. Therefore, at least one of the optional reads or writes of the SPI Data Register must
take place, in order to clear the SPIF status bit.
Read Overrun
A read overrun occurs when the SPI block internal read buffer contains data that has not
been read by the processor, and a new transfer has completed. The read buffer
containing valid data is indicated by the SPIF bit in the SPI Interrupt Register being active.
When a transfer completes, the SPI block needs to move the received data to the read
buffer. If the SPIF bit is active (the read buffer is full), the new receive data will be lost, and
the read overrun (ROVR) bit in the SPI Status Register will be activated.
Write Collision
As stated previously, there is no write buffer between the SPI block bus interface, and the
internal shift register. As a result, data must not be written to the SPI Data Register when
a SPI data transfer is currently in progress. The time frame where data cannot be written
to the SPI Data Register is from when the transfer starts, until after the SPI Status
3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set
4. Read the SPI Status Register.
5. Read the received data from the SPI Data Register (optional).
6. Go to step 2 if more data is to be transmitted.
1. Set the SPI Control Register to the desired settings for slave mode.
1. Optionally, verify the SPI setup before starting the transfer.
2. Write the data to transmitted to the SPI Data Register (optional). Note that this can
3. Wait for the SPIF bit in the SPI Status Register to be set to 1. The SPIF bit will be set
4. Read the SPI Status Register.
5. Read the received data from the SPI Data Register (optional).
6. Go to step 2 if more data is to be transferred.
after the last cycle of the SPI data transfer.
only be done when a slave SPI transfer is not in progress.
after the last sampling clock edge of the SPI data transfer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 17: LPC17xx SPI
UM10360
© NXP B.V. 2010. All rights reserved.
405 of 840
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