LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 600
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 559. DMA Request Select register (DMAReqSel - 0x400F C1C4)
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
31:8
Name
DMASEL08
DMASEL09
DMASEL10
DMASEL11
DMASEL12
DMASEL13
DMASEL14
DMASEL15
-
31.5.15 DMA Request Select register (DMAReqSel - 0x400F C1C4)
31.5.16 DMA Channel registers
DMAReqSel is a read/write register that allows selecting between UART or Timer DMA
requests for DMA inputs 8 through 15.
DMAReqSel Register.
The channel registers are used to program the eight DMA channels. These registers
consist of:
When performing scatter/gather DMA, the first four of these are automatically updated.
•
•
•
•
•
Eight DMACCxSrcAddr Registers.
Eight DMACCxDestAddr Registers.
Eight DMACCxLLI Registers.
Eight DMACCxControl Registers.
Eight DMACCxConfig Registers.
Function
Selects the DMA request for GPDMA input 8:
0 - UART0 TX is selected.
1 - Timer 0 match 0 is selected.
Selects the DMA request for GPDMA input 9:
0 - UART0 RX is selected.
1 - Timer 0 match 1 is selected.
Selects the DMA request for GPDMA input 10:
0 - UART1 TX is selected.
1 - Timer 1match 0 is selected.
Selects the DMA request for GPDMA input 11:
0 - UART1 RX is selected.
1 - Timer 1match 1 is selected.
Selects the DMA request for GPDMA input 12:
0 - UART2 TX is selected.
1 - Timer 2 match 0 is selected.
Selects the DMA request for GPDMA input 13:
0 - UART2 RX is selected.
1 - Timer 2 match 1 is selected.
Selects the DMA request for GPDMA input 14:
0 - UART3 TX is selected.
1 - Timer 3 match 0 is selected.
Selects the DMA request for GPDMA input 15:
0 - UART3 RX is selected.
1 - Timer 3 match 1 is selected.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 559
shows the bit assignments of the
UM10360
© NXP B.V. 2010. All rights reserved.
600 of 840
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