LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 255

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
11.15.1 Transfer terminology
11.15.2 USB device communication area
Section 11.15.4 “The DMA
Section 11.15.5 “Non-isochronous endpoint
endpoint
operation”.
Within this section three types of transfers are mentioned:
The CPU and DMA controller communicate through a common area of memory, called the
USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA
Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP
points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs
for unrealized endpoints and endpoints disabled for DMA operation are ignored and can
be set to a NULL (0x0) value.
The start address of the UDCA is stored in the USBUDCAH register. The UDCA can
reside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA
controller.
Figure 30
register and DMA Descriptors.
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
(RAM).
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.
operation”, and
illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 11.15.7 “Auto Length Transfer Extraction (ATLE) mode
descriptor”. The last three sections describe DMA operation:
Chapter 11: LPC17xx USB device controller
operation”,
Section 11.15.6 “Isochronous
UM10360
© NXP B.V. 2010. All rights reserved.
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